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Entry  Thu Dec 23 03:42:26 2021, Lynsey, DRS4 request assistance 
    Reply  Mon Jan 3 17:13:41 2022, Stefan Ritt, DRS4 request assistance 
Message ID: 855     Entry time: Mon Jan 3 17:13:41 2022     In reply to: 853
Author: Stefan Ritt 
Subject: DRS4 request assistance 

1. fDOMINO is defined as fREFCLK * 2048

2. Good values can be derived from the evaluation board schematics: C1=4.7nF, C2=1nF, R=130 Ohm

3. A "1" means a logical high level. See Wikipedia: https://en.wikipedia.org/wiki/Logic_level

Lynsey wrote:

Dear Sir or Madam,

      Good morning,I am using drs4 chip, and the measured fDTAP == 1/350ns, that is, fDOMINO == 1 / 350ns * 2048 == 5.8GHz.

     I have three questions:

                              1. Is fDOMINO determined by the chip itself?

                              2. C1, C2 and R2 are TBD. I don't know how many to choose. Is there an algorithm?

                              3."Configure Write Shift Register to contain all 1's",What, pray, is the meaning of “1's"?

                                                                                                                                                          Truely yours.



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