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Hello
I'm working to bring up a new capture board using a DRS4 and I'm having a minor problem and a major problem.
Minor problem: if I send a reset signal into the DRS4, the PLL doesn't work right. If I leave NRSESET pin with a wek pullup (and never 'manually' reset the DRS4) it runs OK. Is there some minimum time I need to observe between sending a NRESET pulse and setting DENABLE high to start the PLL?
Major problem: I can't get the stop position.
What am I doing?
- Set DENABLE high
- Wait until DRS capture is requested (seconds to minutes)
- Configure Write Shift Register with 0b01010101
- Configure Write Control Register with 0b11111111
- Fill the Read Shift Register with 1024x '0's
- Set DWRITE high
- Await trigger (some milliseconds). During this phase address = 0b1011
- Set DWRITE low
- Wait ~ 40 ns
- Set address = 0b1101
- Wait ~ 150 us
- Pulse RSRLOAD high for 30 ns
- Wait 30 ns
- Sample SROUT to get top bit of Write Shift Register
- Set address = 0b0000
- Wait ~ 350 ns
- Begin clocking out analog samples
What's going wrong?
- When I look at the first 10 bits out of SROUT, I should see stop positions. However, these bits are almost always zero (I get 7 bits which are always 0 followed by 3 bits which are sometimes ones)
- When I probe the WSROUT pin (and remembering that DWRITE is low at this point), I expected to see a single one bit coming out of the read shift register as I apply 1024 pulses to SRCLK. Instead, I am seeing two set bits coming out of the read shift register
- When I plot the captured analog waveform it's a mess - it seems like 2 analog output buffers are enabling at once and fighting over the output voltage
Do you have any suggestions or warnings about proper deployment of the RSRLOAD pin?
I left this a bit late in my day for posting, so I'll need to follow up with some 'scope captures tomorrow.
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