DRS4 Forum
  DRS4 Discussion Forum  Not logged in ELOG logo
 Back  |  Find  |  Login  |  Help 
Entry  Tue Jun 22 10:50:19 2010, Jinhong Wang, Reset of DRS4 
    Reply  Tue Jun 22 11:02:30 2010, Stefan Ritt, Reset of DRS4 
       Reply  Tue Jun 22 11:29:26 2010, Jinhong Wang, Reset of DRS4 
          Reply  Tue Jun 22 11:35:18 2010, Stefan Ritt, Reset of DRS4 
             Reply  Tue Jun 22 11:37:42 2010, Jinhong Wang, Reset of DRS4 
Message ID: 97     Entry time: Tue Jun 22 11:35:18 2010     In reply to: 96     Reply to this: 98
Author: Stefan Ritt 
Subject: Reset of DRS4 

Jinhong Wang wrote:

Stefan Ritt wrote:

Jinhong Wang wrote:

 Hi Stefan, 

      I found DRS draw a lot of current when applied Reset after power on,  and the PLL does not work properly. I believe there was something that I misunderstood. So,  what will happen when Reset is applied more than once after power on? . Though the chip worked well without a Reset,   i want to try to find out what was wrong, for a better understanding of DRS. 

     best regards!

           Jinhong

Have you made sure that DENABLE and DWRITE stays low during the reset? 

 Yes, they are stay low until Reset goes high. the process is as following

   Step1: Reset ='1', DEnable ='0', DWrite ='0', Reg_addr ="1111", Rsload='0', Srin ='0'

  Step2: Reset='0', the others do not change, the low of the pulse is longer than 10 ns.

  Step3: Reset='1', the others do not change, wait for some time

  Step4:  DEnable ='1' to start the domino.

Ok, then I have no idea. I never tried several reset pulses (actually this is not needed), so I have to reproduce the problem myself and investigate it. Actually in all my designs the reset input is just left open, since the internal initial reset is enough, so I have to modify my design first... 

ELOG V3.1.5-fe60aaf