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Entry  Mon Oct 19 09:06:43 2009, Jinhong Wang, BIAS Pin of DRS4 
    Reply  Mon Oct 19 09:13:00 2009, Stefan Ritt, BIAS Pin of DRS4 
Message ID: 18     Entry time: Mon Oct 19 09:13:00 2009     In reply to: 17
Author: Stefan Ritt 
Subject: BIAS Pin of DRS4 

Jinhong Wang wrote:

Dear Mr. Stefan Ritt.

         Thank u for your timely response on "DSR4 Full Readout Mode", I received it from Professor Qi An, who is my PhD supervisor.

        I am currently going through the DRS4 datasheet. Well, can you give some specification on the usage of "BIAS" pin of DRS4? It is just metioned in the datasheet as bias of internal buffer. What is the internal buffer exactly reffered to here? The MUXOUT buffer of channel 8 or else? Does it have some relationship to O_OFS? I mean, if the reference voltage to BIAS is changed, how will the output be influenced?

       Looking forward to hearing from you soon.

                                                                       Jinhong Wang

                                                                    Fast Electronics LAB. of University of Science and Technology of China.

"internal buffers" are all internal operational amplifiers in the DRS4 chip. Every OPAMP needs a bias (just look it up in any electronics textbook), which determines the linearity and the speed of the OPAMP. When designing DRS4, I was not sure if the required BIAS voltage changes over time, or between chips, so I made it available at a pin, which is a common technique in chip design. But it turns out now that this voltage is not very critical, so just keeping the pin open will work in most cases. 

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