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DRS4 Forum
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| DRS4 Discussion Forum |
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 Thu Nov 1 20:08:33 2012, hongwei yang, DRS4 firmware
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 Thu Nov 1 20:17:42 2012, Stefan Ritt, DRS4 firmware 
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Thu Nov 1 20:21:44 2012, hongwei yang, DRS4 firmware
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Thu Nov 1 20:25:53 2012, hongwei yang, DRS4 firmware
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Thu Nov 1 20:32:03 2012, Stefan Ritt, DRS4 firmware
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Thu Nov 1 20:46:53 2012, hongwei yang, DRS4 firmware
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Message ID: 190
Entry time: Thu Nov 1 20:32:03 2012
In reply to: 189
Reply to this: 191
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| Author: |
Stefan Ritt |
| Subject: |
DRS4 firmware |
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| hongwei yang wrote: |
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| hongwei yang wrote: |
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| Stefan Ritt wrote: |
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| hongwei yang wrote: |
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Hi,
We are using drs4 board, but oscilloscope app will somehow stop to work if we config trigger into "or and", When I look into the drs4 firmware file drs4_eval3_app.vhd, I couldn't find the trigger_config value assignment which is mentioned at(#7 offset 0x1E from 31 downto 16) in manual_version 4.
could you help me find this trigger_config access point?
thanks
Hongwei
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The "and" in the trigger section means now "coincidence". So the V4 board can trigger on a coincidence between two or more channels. If there is no pulse at the same time on the coincidence channels, the board will of course not trigger. The according firmware was introduced in V4, so please look at drs4_eval4_app.vhd (not eval3).
I just realized that the V4 firmware might be missing in the distribution, so I have attached it here. Look for drs_ctl_trigger_config.
Best regards,
Stefan
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Ah, great, that helps, Thank you!
Hongwei
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By the way, will there be a drs4_eval4.vhd as well?
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Here it is. |
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--#############################################################
-- Author : Stefan Ritt
-- Contents : DRS4 Evaluation Board FPGA top level entity
-- $Id: drs4_eval4.vhd 13988 2009-08-03 15:28:19Z ritt $
--#############################################################
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.drs4_pack.all;
entity drs4_eval4 is
port (
-- Quartz
P_I_CLK33 : in std_logic;
P_I_CLK66 : in std_logic;
-- Test points
P_IO_J45 : inout std_logic;
P_IO_J46 : inout std_logic;
P_I_J47 : in std_logic;
P_IO_J48 : inout std_logic;
P_IO_J49 : inout std_logic;
-- analog triggers
P_I_ATRG1 : in std_logic;
P_I_ATRG2 : in std_logic;
P_I_ATRG3 : in std_logic;
P_I_ATRG4 : in std_logic;
-- external trigger
P_IO_ETRG_IN : inout std_logic;
P_O_ETRG_IND : out std_logic;
P_IO_ETRG_OUT : inout std_logic;
P_O_ETRG_OUTD : out std_logic;
-- external (MMCX clock) clock
P_IO_ECLK_IN : inout std_logic;
P_O_ECLK_IND : out std_logic;
P_IO_ECLK_OUT : inout std_logic;
P_O_ECLK_OUTD : out std_logic;
-- LEDs
P_O_LED0 : out std_logic;
P_O_LED1 : out std_logic;
-- Lines to/from Cy7C68013A microcontroller
P_IO_UC_SLOE : inout std_logic;
P_IO_UC_SLRD : inout std_logic;
P_IO_UC_SLWR : inout std_logic;
P_IO_UC_SLCS : inout std_logic;
P_IO_UC_PKTEND : inout std_logic;
P_IO_UC_FIFOADR0 : inout std_logic;
P_IO_UC_FIFOADR1 : inout std_logic;
P_IO_UC_FLAGA : inout std_logic;
P_IO_UC_FLAGB : inout std_logic;
P_IO_UC_FLAGC : inout std_logic;
P_I_UC_PA0 : in std_logic;
P_IO_UC_FD : inout std_logic_vector(15 downto 0);
-- PMC connector
P_IO_PMC_USR : inout std_logic_vector(63 downto 0)
);
end drs4_eval4;
architecture arch of drs4_eval4 is
component usr_clocks
port (
P_I_CLK33 : in std_logic;
P_I_CLK66 : in std_logic;
O_CLK33 : out std_logic;
O_CLK33_NODLL : out std_logic;
O_CLK66 : out std_logic;
O_CLK132 : out std_logic;
O_CLK264 : out std_logic;
I_PS_VALUE : in std_logic_vector(7 downto 0);
O_CLK_PS : out std_logic;
O_LOCKED : out std_logic;
O_DEBUG1 : out std_logic;
O_DEBUG2 : out std_logic
);
end component;
component usb2_racc is
port (
-- Clock signals
-- ------------------------
I_RESET : in std_logic;
I_CLK33 : in std_logic;
-- Lines to/from Cy7C68013A microcontroller
-- -----------------------------------
P_IO_UC_SLOE : inout std_logic;
P_IO_UC_SLRD : inout std_logic;
P_IO_UC_SLWR : inout std_logic;
P_IO_UC_SLCS : inout std_logic;
P_IO_UC_PKTEND : inout std_logic;
P_IO_UC_FIFOADR0 : inout std_logic;
P_IO_UC_FIFOADR1 : inout std_logic;
P_IO_UC_FLAGA : inout std_logic;
P_IO_UC_FLAGB : inout std_logic;
P_IO_UC_FLAGC : inout std_logic;
P_IO_UC_FD : inout std_logic_vector(15 downto 0);
-- Simple bus interface to on-chip RAM
-- --------------------------------------------------
O_LOCBUS_ADDR : out std_logic_vector(31 downto 0);
I_LOCBUS_D_RD : in std_logic_vector(31 downto 0);
O_LOCBUS_D_WR : out std_logic_vector(31 downto 0);
O_LOCBUS_WE : out std_logic;
-- Status & control registers
-----------------------------
O_CONTROL_REG_ARR : out type_control_reg_arr;
I_STATUS_REG_ARR : in type_status_reg_arr;
O_CONTROL_TRIG_ARR : out type_control_trig_arr;
O_CONTROL0_BIT_TRIG_ARR : out std_logic_vector(31 downto 0);
-- Debug signals
-- -------------
O_DEBUG : out std_logic
);
end component;
component usb_dpram is
port (
I_RESET : in std_logic;
I_CLK_A : in std_logic;
I_ADDR_A : in std_logic_vector(31 downto 0);
I_WE_A : in std_logic;
O_D_RD_A : out std_logic_vector(31 downto 0);
I_D_WR_A : in std_logic_vector(31 downto 0);
I_CLK_B : in std_logic;
I_ADDR_B : in std_logic_vector(31 downto 0);
I_WE_B : in std_logic;
O_D_RD_B : out std_logic_vector(31 downto 0);
I_D_WR_B : in std_logic_vector(31 downto 0)
);
end component;
component drs4_eval4_app is
port (
I_CLK33 : in std_logic; -- 33 MHz, sychronised to clk33_nodll
I_CLK66 : in std_logic; -- 66 MHz, same phase as clk33
I_CLK132 : in std_logic; -- 132 MHz, random phase in respect to clk33
I_CLK264 : in std_logic; -- 264 MHz, random phase in respect to clk33
O_CLK_PS_VALUE : out std_logic_vector(7 downto 0); -- value for phase shift
I_CLK_PS : in std_logic; -- phase shifted in respect to clk33
I_RESET : in std_logic; -- active high power-up reset
-- analog triggers
I_ANA_TRG : in std_logic_vector(3 downto 0);
-- external trigger
IO_ETRG_IN : inout std_logic;
O_ETRG_IND : out std_logic;
IO_ETRG_OUT : inout std_logic;
O_ETRG_OUTD : out std_logic;
-- external (MMCX clock) clock
IO_ECLK_OUT : inout std_logic;
IO_ECLK_IN : inout std_logic;
-- PMC
P_IO_PMC_USR : inout std_logic_vector(63 downto 0);
-- Simple bus interface to DPRAM
O_DPRAM_CLK : out std_logic;
O_DPRAM_ADDR : out std_logic_vector(31 downto 0);
O_DPRAM_D_WR : out std_logic_vector(31 downto 0);
O_DPRAM_WE : out std_logic;
I_DPRAM_D_RD : in std_logic_vector(31 downto 0);
-- Control & status registers from system FPGA interface
I_CONTROL_REG_ARR : in type_control_reg_arr;
O_STATUS_REG_ARR : out type_status_reg_arr;
I_CONTROL_TRIG_ARR : in type_control_trig_arr;
I_CONTROL0_BIT_TRIG_ARR : in std_logic_vector(31 downto 0);
-- LEDs signals
O_LED_RED : out std_logic;
O_LED_YELLOW : out std_logic;
-- Debug signals
O_DEBUG1 : out std_logic;
O_DEBUG2 : out std_logic
);
end component;
signal VCC: std_logic;
signal GND: std_logic;
-- reset signal
-- -------------
signal global_reset : std_logic; -- active high power-up reset
-- clocks & related signals
-- ------------------------
signal clk33_nodll : std_logic; -- external 33 MHz clock (global clock net)
signal clk33 : std_logic; -- 33 MHz DLL output
signal clk66 : std_logic;
signal clk132 : std_logic;
signal clk264 : std_logic;
signal clk_ps_value : std_logic_vector(7 downto 0);
signal clk_ps : std_logic; -- special phase shifted clock
signal usr_clks_dlls_locked : std_logic; -- high if clock DLLs for clkxx have locked
-- user application signals for Locbus interface
-- ---------------------------------------------
signal locbus_addr : std_logic_vector(31 downto 0);
signal locbus_d_rd : std_logic_vector(31 downto 0);
signal locbus_d_wr : std_logic_vector(31 downto 0);
signal locbus_we : std_logic;
-- user application signals for DPRAM interface
-- --------------------------------------------
signal dpram_clk : std_logic;
signal dpram_addr : std_logic_vector(31 downto 0);
signal dpram_we : std_logic;
signal dpram_d_wr : std_logic_vector(31 downto 0);
signal dpram_d_rd : std_logic_vector(31 downto 0);
-- register signals for data exchange with microcontroller
-- -------------------------------------------------------
signal control_reg_arr : type_control_reg_arr;
signal status_reg_arr : type_status_reg_arr;
signal control_trig_arr: type_control_trig_arr;
signal control0_bit_trig_arr : std_logic_vector(31 downto 0);
-- LEDs
-- ----
signal o_led_red : std_logic;
signal o_led_yellow : std_logic;
-- Trigger
-- -------
signal io_etrg_in : std_logic;
signal o_etrg_ind : std_logic;
signal io_etrg_out : std_logic;
signal o_etrg_outd : std_logic;
signal i_ana_trg : std_logic_vector(3 downto 0);
signal io_eclk_out : std_logic;
signal io_eclk_in : std_logic;
-- Debugging signals
-- -----------------
signal o_racc_debug : std_logic;
signal o_debug1 : std_logic;
signal o_debug2 : std_logic;
begin
VCC <= '1';
GND <= '0';
-- map LEDs
P_O_LED0 <= o_led_yellow;
P_O_LED1 <= o_led_red;
-- debug outputs
P_IO_J45 <= GND;
P_IO_J46 <= GND;
P_IO_J48 <= o_debug1;
P_IO_J49 <= o_debug2;
-- triggers
i_ana_trg(0) <= P_I_ATRG1;
i_ana_trg(1) <= P_I_ATRG2;
i_ana_trg(2) <= P_I_ATRG3;
i_ana_trg(3) <= P_I_ATRG4;
io_etrg_in <= P_IO_ETRG_IN;
P_O_ETRG_IND <= o_etrg_ind;
P_IO_ETRG_OUT <= io_etrg_out;
P_O_ETRG_OUTD <= o_etrg_outd;
-- external clock
P_IO_ECLK_OUT <= io_eclk_out;
P_O_ECLK_OUTD <= '1';
io_eclk_in <= P_IO_ECLK_IN;
P_O_ECLK_IND <= '0';
clocks : usr_clocks port map (
P_I_CLK33 => P_I_CLK33,
P_I_CLK66 => P_I_CLK66,
O_CLK33 => clk33,
O_CLK33_NODLL => clk33_nodll,
O_CLK66 => clk66,
O_CLK132 => clk132,
... 121 more lines ...
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