DRS4 Forum
  DRS4 Discussion Forum  Not logged in ELOG logo
Entry  Wed Oct 15 10:14:32 2014, Simon Weingarten, Clock settings in daisy chain DAQ 
    Reply  Wed Oct 15 10:52:58 2014, Stefan Ritt, Clock settings in daisy chain DAQ 
       Reply  Wed Oct 15 11:34:43 2014, Simon Weingarten, Clock settings in daisy chain DAQ 
       Reply  Wed Oct 15 12:15:58 2014, Stefan Ritt, Clock settings in daisy chain DAQ drs_exam_multi.cpp
          Reply  Fri Apr 17 10:07:38 2015, Simon Weingarten, Clock settings in daisy chain DAQ 
             Reply  Mon Apr 20 13:08:24 2015, Stefan Ritt, Clock settings in daisy chain DAQ 
Message ID: 403     Entry time: Fri Apr 17 10:07:38 2015     In reply to: 389     Reply to this: 404
Author: Simon Weingarten 
Subject: Clock settings in daisy chain DAQ 

Hi Stefan,

do you know how these numbers (400ps and 60ps) scale with the sampling rate? The manual says they are for 5GS/s, do they change with slower sampling?

Thanks and best regards,

Simon

Stefan Ritt wrote:

Here is the full version of the program with clock daisy-chaining. Before switching to the external clock, it checks if the clock really is there (by reading an internal scaler), and only then enables it. Note that the code also works without clock daisy-chaining. But without clock daisy-chaining your have some 400 ps time resolution between boards, and with clock daisy-chaining you get some 60 ps.

 

ELOG V3.1.4-80633ba