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 Wed May 13 09:31:18 2015, Chenfei Yang, transparent-mode voltage Wed May 13 09:45:51 2015, Stefan Ritt, transparent-mode voltage Wed May 13 09:55:09 2015, Chenfei Yang, transparent-mode voltage Wed May 13 10:16:40 2015, Stefan Ritt, transparent-mode voltage Wed May 13 10:27:43 2015, Chenfei Yang, transparent-mode voltage Wed May 13 12:34:49 2015, Stefan Ritt, transparent-mode voltage Wed May 13 12:52:22 2015, Chenfei Yang, transparent-mode voltage Wed May 13 16:13:07 2015, Chenfei Yang, transparent-mode voltage Wed May 13 16:25:24 2015, Stefan Ritt, transparent-mode voltage
Message ID: 417     Entry time: Wed May 13 12:34:49 2015     In reply to: 415     Reply to this: 418   419
 Author: Stefan Ritt Subject: transparent-mode voltage

There might be a solution. How do you bias th input of the DRS4 chip? If you use a scheme as described in elog:84, you can bias DRS_IN+ and DRS_IN- as desired. Take for example a board input range of 0-1V. For a 0V input, you bias DRS_IN+ and DRS_IN- both with 0.9V. A 1V input signal then puts DRS_IN+ to 1.4V and DRS_IN-to 0.4 V. In the transparent mode, DRS_OUT+ = DRS_IN+ and DRS_OUT- = O-OFS - DRS_OUT+. So if you put O-OFS to 0.9V, you get for a 0V board input signal DRS_OUT- = 2*0.9V - DRS_OUT+ = 0.9V. So DRS_OUT+   = DRS_OUT- = 0.9 V which is in the middle of your ADC range.

If you do now a DRS readout, you need a ROFS of roughly 0.9V. For a 0V input, the storage capacitors have a zero differential voltage (DRS_IN+ = DRS_IN- = 0.8V), so DRS_OUT+ = (0.8V - 0.8V) + ROFS  = 0.9V, and since you have O-OFS=0.9V, you will also get DRS_OUT- = 2*0.9V - DRS_OUT+ = 0.9V. So you ranges for transparent mode nad DRS readout mode will be roughly the same.

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