Yes this is correct. But it is a sample-and-hold circuit. So the sampling cell follows the input for 3.2 ns, then samples and holds the current value at the end of the period.
I just stumbled again over a phrase in the DRS4 datasheet I never really understood, but didn't find the time to ask.
On page 8 it says: "An internal circuit ensures that the write signal is always 16 cells wide."
So when I look at a single channel, do I understand correctly, that at any given time during sampling, always 16 cells are open, i.e. 16 cells are connected to the analog inputs? So when the domino frequency is e.g. 5GHz then each cell sees the analog input not for 200ps but for 3.2ns correct?