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Entry  Wed Aug 1 00:49:30 2018, Sean Quinn, Optimal readout speed eval51_adc_50ns.png
    Reply  Tue Aug 21 14:36:44 2018, Stefan Ritt, Optimal readout speed 
Message ID: 710     Entry time: Wed Aug 1 00:49:30 2018     Reply to this: 713
Author: Sean Quinn 
Subject: Optimal readout speed 

Dear DRS4 team,

On page 3 of the data sheet, Table 1. for readout speed a typical value of 10 MHz is specified, but in the comment column it notes optimal performance achieved at 33 MHz.

I see the V5.1 eval board runs at 16 MHz. I'd like to understand the rationale for this using speed, instead of 33 MHz. Is there an SNR issue for the ADC at the higher speed, even though this is optimal for the DRS4?

Very best,


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