DRS4 Forum
  DRS4 Discussion Forum  Not logged in ELOG logo
Entry  Wed Aug 1 00:49:30 2018, Sean Quinn, Optimal readout speed eval51_adc_50ns.png
    Reply  Tue Aug 21 14:36:44 2018, Stefan Ritt, Optimal readout speed 
Message ID: 713     Entry time: Tue Aug 21 14:36:44 2018     In reply to: 710
Author: Stefan Ritt 
Subject: Optimal readout speed 

The analog output of the DRS4 chip needs some time to settle. In principle it need an infinite amout of time (exponential curve) to settle to 100% of the final value. So if we sample after a finite time, there is some error we do. Some of the error will be taken care of the voltage calibration, but there remains some residual error depending on the value of the previous sampling cell. So all sampling speeds 10 MHz, 16 MHz, 33 MHz are kind of rule of thumbs. In the end we run the evaluation board at 16 MHz to save a little bit of power (which is limited on an USB device). But I never made a careful study of noise-after-calibration vs. sampling speed. If you have some measurements, I'm happt to include it in the data sheet.


Sean Quinn wrote:

Dear DRS4 team,

On page 3 of the data sheet, Table 1. for readout speed a typical value of 10 MHz is specified, but in the comment column it notes optimal performance achieved at 33 MHz.

I see the V5.1 eval board runs at 16 MHz. I'd like to understand the rationale for this using speed, instead of 33 MHz. Is there an SNR issue for the ADC at the higher speed, even though this is optimal for the DRS4?

Very best,



ELOG V3.1.4-bcd7b50