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Entry  Thu May 13 19:14:27 2010, Hao Huan, DVDD Problem of DRS 4 
    Reply  Fri May 14 08:40:14 2010, Stefan Ritt, DVDD Problem of DRS 4 
       Reply  Tue May 18 01:47:59 2010, Hao Huan, DVDD Problem of DRS 4 
          Reply  Tue May 18 08:23:07 2010, Stefan Ritt, DVDD Problem of DRS 4 
             Reply  Wed May 19 02:24:12 2010, Hao Huan, DVDD Problem of DRS 4 
                Reply  Wed May 19 09:16:02 2010, Stefan Ritt, DVDD Problem of DRS 4 
                   Reply  Fri Jun 18 11:31:20 2010, Jinhong Wang, DVDD Problem of DRS 4 
                      Reply  Fri Jun 18 11:45:18 2010, Stefan Ritt, DVDD Problem of DRS 4 
                         Reply  Sat Jun 19 10:09:18 2010, Jinhong Wang, DVDD Problem of DRS 4 
Message ID: 91     Entry time: Fri Jun 18 11:31:20 2010     In reply to: 86     Reply to this: 92
Author: Jinhong Wang 
Subject: DVDD Problem of DRS 4 

Stefan Ritt wrote:

Hao Huan wrote:

Stefan Ritt wrote:

Hao Huan wrote:

Stefan Ritt wrote:

Hao Huan wrote:

Hi Stefan,

    on our board some DRS chips draw a lot of current through DVDD after power-up and heat up significantly--it is true that our board doesn't have weak pull-down resistors at DENABLE and DWRITE output pins of FPGA, so this problem might have been caused by that, but a reinitialization of the Domino circuit doesn't help either. We tried different capacitors at DVDD and it seemed the larger the capacitance, the better the result--with a capacitor larger than 10nF some of the DRS chips could work happily in the normal way while if the capacitor is only 4.7nF all of them got very hot. Would you please provide some suggestions why there should be such a problem?

    Thanks a lot!

I found that sometimes even a reinitialization fails if the pull-down resistors are missing. So instead playing with capacitors at DVDD, I would just solder two resistors on the board which should fix the problem completely.

 Thanks! After adding pull-down resistors the voltages come back to normal.

However there is another weird problem that arises: a reset pulse seems unable to set the internal shift registers to default values. For example, after reset without addressing the Config Register the PLL will not try to lock with external reference clock. Even if I explicitly address the Config Register after reset and have the PLL locked, some channels of the chip will give null output during readout while other channels work normally. Could it be that some channels are not initiated properly with the Domino circuit?

Something is wrong. I have 800 chips, and they all start up fine. Check with your scope the RESET, DSPEED, DENABLE and DTAP signals. When RESET is applied, DSPEED should go to 2.5 V. When DENABLE goes high, the domino wave is started and you should see DTAP toggle. DSPEED is then lowered by the PLL until DTAP matches your external reference clock. I usually keep DENABLE high all the time after initialization, so the domino wave just continues running.

Another problem could however be the chip readout. If some channel gives null output, it could be that your readout has a problem. Do you use RSRLOAD to initialize the readout sequence?

 Yes; I used RSRLOAD to trigger readout of all channels in parallel so the asymmetry between channels of the same chip is really a big puzzle. Also during reset DSPEED indeed goes to 2.5V, but after reset the PLL will not try to lock with the external reference clock and lower DSPEED. Instead the Domino circuit just oscillates at the highest frequency by itself.

A more confusing discovery is that the SRIN level before starting the Domino wave could affect the behavior of the PLL. I mean the level of SRIN when the chip is at A="1111" or "1010". Is SRIN supposed to influence the chip even in these standby or transparent modes?

Just some ideas:

  • Is DENABLE really kept high all the time?
  • Is DRESET only applied once during initialization, after that it should stay high
  • Does  REFCLK+/REFCLK- really toggle at the required sampling speed / 2048?
  • Is the REFCLK really a good differential signal? Note that it must be biased properly since the DRS4 inputs are high impedance
  • Is the Bit1 in the Config Register really at "1" to enable the PLL?

The only way the SRIN level could affect the PLL is if you address the Config Register (A="1100") and you clock in a few bits with SRCLK.

Have you thought about 'crazy' things such as:

  • Defining the DRS4 chip wronly in your CAD software so that the pins are different from what you think?
  • Some soldering problem of the DRS4 chips (we had this in the past) so that some pins are not connected at all and others have shorts

I guess you checked most of the things, so I'm just wildly guessing in order to stimulate some thoughts.

The ultimate check would be to get one of the evaluation boards (I sent a few to Jean-Francois Genat some time ago...) and compare the DRS4 signals pin by pin.

 Hi Stefan

       I designed the evaluation board for our experiment. On our boards, I  encountered the similar problem when working on the PLL of DRS4. I compared the following two configuration process, which on with PLL locked, the other not,

   Process1: 

       step 1: Set DEnable and DWrite low, 

      Step2 : Reset DRS4 with a negative pulse of about 900 ns

      Step3: Set DEnable high,  thus do nothing but wait

       I found DRS4 PLL working and locked. 

  

  Process 2:

   Step 1: Set DEnable and DWrite low, 

  Step2 : Reset DRS4 with a negative pulse of about 900 ns 

  Step3: Set Config. Register( "11111111" .of course, this step was not necessary, just to see whether SPI was working properly from DTAP when set to "11111110")

  Step4: Set The read shift Register ( full read out mode)

  Step5: Set DEnable high, 

  Step6: Set DWrite high  , thus low it , and prepare to read the waveform.

  Well, I found in this case, the PLL was not locked, I am sure there was no problem with my SPI configuration process of DRS4. 

  toggle from DTAP could be viewed, but not stable. 

 Any Suggestions ?

  thanks.

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