DRS4 Forum
  DRS4 Discussion Forum  Not logged in ELOG logo
Entry  Thu May 13 19:14:27 2010, Hao Huan, DVDD Problem of DRS 4 
    Reply  Fri May 14 08:40:14 2010, Stefan Ritt, DVDD Problem of DRS 4 
       Reply  Tue May 18 01:47:59 2010, Hao Huan, DVDD Problem of DRS 4 
          Reply  Tue May 18 08:23:07 2010, Stefan Ritt, DVDD Problem of DRS 4 
             Reply  Wed May 19 02:24:12 2010, Hao Huan, DVDD Problem of DRS 4 
                Reply  Wed May 19 09:16:02 2010, Stefan Ritt, DVDD Problem of DRS 4 
                   Reply  Fri Jun 18 11:31:20 2010, Jinhong Wang, DVDD Problem of DRS 4 
                      Reply  Fri Jun 18 11:45:18 2010, Stefan Ritt, DVDD Problem of DRS 4 
                         Reply  Sat Jun 19 10:09:18 2010, Jinhong Wang, DVDD Problem of DRS 4 
Message ID: 93     Entry time: Sat Jun 19 10:09:18 2010     In reply to: 92
Author: Jinhong Wang 
Subject: DVDD Problem of DRS 4 

Stefan Ritt wrote:

Jinhong Wang wrote:

 

 Hi Stefan

       I designed the evaluation board for our experiment. On our boards, I  encountered the similar problem when working on the PLL of DRS4. I compared the following two configuration process, which on with PLL locked, the other not,

   Process1: 

       step 1: Set DEnable and DWrite low, 

      Step2 : Reset DRS4 with a negative pulse of about 900 ns

      Step3: Set DEnable high,  thus do nothing but wait

       I found DRS4 PLL working and locked. 

  

  Process 2:

   Step 1: Set DEnable and DWrite low, 

  Step2 : Reset DRS4 with a negative pulse of about 900 ns 

  Step3: Set Config. Register( "11111111" .of course, this step was not necessary, just to see whether SPI was working properly from DTAP when set to "11111110")

  Step4: Set The read shift Register ( full read out mode)

  Step5: Set DEnable high, 

  Step6: Set DWrite high  , thus low it , and prepare to read the waveform.

  Well, I found in this case, the PLL was not locked, I am sure there was no problem with my SPI configuration process of DRS4. 

  toggle from DTAP could be viewed, but not stable. 

 Any Suggestions ?

  thanks.

So the main difference, if I understand correctly, is the setting of the Config Register. Actually I never tried that, I always went with the default settings (all "1"). What happens if you write "00000000"? You know Bit1 controls the PLL, maybe there is a bug and the signal needs to be inverted. 

 Hi, Stefan,

       The problem was fixed by setting Reg_addr "1001" instead of "1111" when in idle state, I was confused. 

ELOG V3.1.4-80633ba