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  797   Tue Sep 22 17:45:26 2020 Elmer GrundemanExternal triggering

Dear all,

I had a question about timing jitter and external triggering.

I trigger the board externally with a 3V pulse from a DG645 delay generator and as a test I use the gated charge function to integrate another pulse of the DG which goes into channel 1 (the timing jitter between different outputs of the DG is on the order of ~25 picoseconds).

The issue I’m encountering is that the signal on channel 1 is jittering in time with ~1 ns, which means the signal is jittering with respect to my integration gate (point A and B). If I look at the data it always starts at t = 0.000 but my signal (pulse) moves around in time.

If I don’t use the external trigger but trigger on channel 1 directly the signal does not move with respect to the gate, but I can see the start and end of the trace move in time. If I look at the data the first data point is not at t = 0.000 but some other time, which jitters with ~1 ns.

I did repeat the voltage and timing calibration, but that did not help either.

Do you know where this jitter comes from and if I can get rid of it?

Best regards,

 

Elmer

  798   Wed Oct 7 10:56:03 2020 Stefan RittExternal triggering

The trigger is there only to trigger the chip, but cannot be used as a precise time reference. If you want to measure precise timing, do this always BETWEEN two inputs, never between an input and the trigger. You might want to split and delay your trigger signal and feed one copy to another input of the evaluation board as your reference.

Stefan

Elmer Grundeman wrote:

Dear all,

I had a question about timing jitter and external triggering.

I trigger the board externally with a 3V pulse from a DG645 delay generator and as a test I use the gated charge function to integrate another pulse of the DG which goes into channel 1 (the timing jitter between different outputs of the DG is on the order of ~25 picoseconds).

The issue I’m encountering is that the signal on channel 1 is jittering in time with ~1 ns, which means the signal is jittering with respect to my integration gate (point A and B). If I look at the data it always starts at t = 0.000 but my signal (pulse) moves around in time.

If I don’t use the external trigger but trigger on channel 1 directly the signal does not move with respect to the gate, but I can see the start and end of the trace move in time. If I look at the data the first data point is not at t = 0.000 but some other time, which jitters with ~1 ns.

I did repeat the voltage and timing calibration, but that did not help either.

Do you know where this jitter comes from and if I can get rid of it?

Best regards,

 

Elmer

 

  799   Wed Oct 7 11:17:52 2020 Elmer GrundemanExternal triggering

I will try that, thanks!

Stefan Ritt wrote:

The trigger is there only to trigger the chip, but cannot be used as a precise time reference. If you want to measure precise timing, do this always BETWEEN two inputs, never between an input and the trigger. You might want to split and delay your trigger signal and feed one copy to another input of the evaluation board as your reference.

Stefan

Elmer Grundeman wrote:

Dear all,

I had a question about timing jitter and external triggering.

I trigger the board externally with a 3V pulse from a DG645 delay generator and as a test I use the gated charge function to integrate another pulse of the DG which goes into channel 1 (the timing jitter between different outputs of the DG is on the order of ~25 picoseconds).

The issue I’m encountering is that the signal on channel 1 is jittering in time with ~1 ns, which means the signal is jittering with respect to my integration gate (point A and B). If I look at the data it always starts at t = 0.000 but my signal (pulse) moves around in time.

If I don’t use the external trigger but trigger on channel 1 directly the signal does not move with respect to the gate, but I can see the start and end of the trace move in time. If I look at the data the first data point is not at t = 0.000 but some other time, which jitters with ~1 ns.

I did repeat the voltage and timing calibration, but that did not help either.

Do you know where this jitter comes from and if I can get rid of it?

Best regards,

 

Elmer

 

 

  800   Wed Oct 21 15:03:13 2020 Seiya NozakiTiming diagram of SROUT/SRIN signal to write/read a write shift register

Dear Stefan,

I have questions about the timing diagram of SROUT/SRIN signal to write/read a write shift register.
1) Value of SRIN signal is saved at the falling edge of SRCLK, correct? (It is written in datasheet, page12, "Bits are latched into the shift register on the falling edge of SRCLK")
2) When are 8-bits of write shift register shown through SROUT? At ridging edges of SRCLK? and with additional delay(~10ns)? or falling edges?
3) In my understanding, when SRCLK is sent to DRS4, we can read and write the values in parallel, right? If so, is it possible just to read the registers without updating the registers?

[Background]
We have two modes to set the write shift register, the first one is to always reconnect to the first line and another one is to reconnect to the same line as when DWRITE goes to Low.
We can read/write the write shift register with the first mode (channel reset, page1). But we rarely face the problem of write shift register, unexpected values are written, with the second mode. With this mode, SROUT signal is sent back to DRS from FPGA as SRIN to write the same value on the write shift register. So there is a small delay(~10ns) due to the routing (DRS->FPGA->DRS, page2). It seems SRIN signal is not stable around the falling edges of SRCLK, thus it could cause that unexpected values are written in write shifter register.
To understand the situation clearly, I'd like to know the answer to the above questions.

Thank you.

Best regards,
Seiya

  801   Tue Oct 27 13:37:23 2020 Stefan RittTiming diagram of SROUT/SRIN signal to write/read a write shift register

Dear Seiya,

1) That's correct. SRIN is ampled at the falling edge. Pleae make sure to obey the hold-time as written in the datasheet. P.12, Fig. 11: SRIN must be stable before the falling edge of SRCLK and tH after the falling clock. tH is 5ns according to table 1. 

2) The write shift register is a 8-bit shift register, with an input, output and clock. After the first clock pulse, the 7th bit is shown, after the second clock pulse the 6th bit and so on. You you need 8 clock pulses to read the whole register. At the same time you write to the register, so what ever is present at SRIN will replace the old 8 bits of that register.

3) No this is not possible. When you read the register, you write to it at the same time. One possibilty is to connect SROUT to SRIN during that (maybe via the FPGA). Then you have a circular register wich is the same after each 8 clock pulses.

For your reference, I posted a commercial D-Flip Flop (TI SNHCS72). The DRS4 write shift register is a simple array of 8 such registers, with no CLR or PRE, where SROUT is Q of the last Flip Flop.

Best,
Stefan

Seiya Nozaki wrote:

Dear Stefan,

I have questions about the timing diagram of SROUT/SRIN signal to write/read a write shift register.
1) Value of SRIN signal is saved at the falling edge of SRCLK, correct? (It is written in datasheet, page12, "Bits are latched into the shift register on the falling edge of SRCLK")
2) When are 8-bits of write shift register shown through SROUT? At ridging edges of SRCLK? and with additional delay(~10ns)? or falling edges?
3) In my understanding, when SRCLK is sent to DRS4, we can read and write the values in parallel, right? If so, is it possible just to read the registers without updating the registers?

[Background]
We have two modes to set the write shift register, the first one is to always reconnect to the first line and another one is to reconnect to the same line as when DWRITE goes to Low.
We can read/write the write shift register with the first mode (channel reset, page1). But we rarely face the problem of write shift register, unexpected values are written, with the second mode. With this mode, SROUT signal is sent back to DRS from FPGA as SRIN to write the same value on the write shift register. So there is a small delay(~10ns) due to the routing (DRS->FPGA->DRS, page2). It seems SRIN signal is not stable around the falling edges of SRCLK, thus it could cause that unexpected values are written in write shifter register.
To understand the situation clearly, I'd like to know the answer to the above questions.

Thank you.

Best regards,
Seiya

 

  802   Tue Oct 27 15:02:09 2020 Seiya NozakiTiming diagram of SROUT/SRIN signal to write/read a write shift register

Dear Stefan,

Thank you for your reply.
SRIN is directly connected to SROUT via FPGA for now, but it is unstable for the timing between clock and SRIN depending on the firmware logic.
We want to make our system more robust, so we are thinking to use a clock with a lower frequency (let's say 16.6 MHz) or change the duty cycle of a clock to keep more time between the rising edge and falling edge of a clock. This change is just for reading/writing the write shift register, we will use a 33 MHz clock for the analog readout in any case.
If we change like above, are there any concerns from the DRS4 side?

Best,
Seiya

Stefan Ritt wrote:

Dear Seiya,

1) That's correct. SRIN is ampled at the falling edge. Pleae make sure to obey the hold-time as written in the datasheet. P.12, Fig. 11: SRIN must be stable before the falling edge of SRCLK and tH after the falling clock. tH is 5ns according to table 1. 

2) The write shift register is a 8-bit shift register, with an input, output and clock. After the first clock pulse, the 7th bit is shown, after the second clock pulse the 6th bit and so on. You you need 8 clock pulses to read the whole register. At the same time you write to the register, so what ever is present at SRIN will replace the old 8 bits of that register.

3) No this is not possible. When you read the register, you write to it at the same time. One possibilty is to connect SROUT to SRIN during that (maybe via the FPGA). Then you have a circular register wich is the same after each 8 clock pulses.

For your reference, I posted a commercial D-Flip Flop (TI SNHCS72). The DRS4 write shift register is a simple array of 8 such registers, with no CLR or PRE, where SROUT is Q of the last Flip Flop.

Best,
Stefan

Seiya Nozaki wrote:

Dear Stefan,

I have questions about the timing diagram of SROUT/SRIN signal to write/read a write shift register.
1) Value of SRIN signal is saved at the falling edge of SRCLK, correct? (It is written in datasheet, page12, "Bits are latched into the shift register on the falling edge of SRCLK")
2) When are 8-bits of write shift register shown through SROUT? At ridging edges of SRCLK? and with additional delay(~10ns)? or falling edges?
3) In my understanding, when SRCLK is sent to DRS4, we can read and write the values in parallel, right? If so, is it possible just to read the registers without updating the registers?

[Background]
We have two modes to set the write shift register, the first one is to always reconnect to the first line and another one is to reconnect to the same line as when DWRITE goes to Low.
We can read/write the write shift register with the first mode (channel reset, page1). But we rarely face the problem of write shift register, unexpected values are written, with the second mode. With this mode, SROUT signal is sent back to DRS from FPGA as SRIN to write the same value on the write shift register. So there is a small delay(~10ns) due to the routing (DRS->FPGA->DRS, page2). It seems SRIN signal is not stable around the falling edges of SRCLK, thus it could cause that unexpected values are written in write shifter register.
To understand the situation clearly, I'd like to know the answer to the above questions.

Thank you.

Best regards,
Seiya

 

 

  803   Tue Oct 27 15:24:38 2020 Stefan RittTiming diagram of SROUT/SRIN signal to write/read a write shift register

This is a static shift register, so you can make the clock as slow as you want. Actually I don't use a "clock", I just use a data pin I control via a state machine in the VHDL code. This way I have more control over the edges. I need several (internal) clock cycles to produce one SRCLK clock cycle, but that does not matter for the DRS.

Stefan

Seiya Nozaki wrote:

Dear Stefan,

Thank you for your reply.
SRIN is directly connected to SROUT via FPGA for now, but it is unstable for the timing between clock and SRIN depending on the firmware logic.
We want to make our system more robust, so we are thinking to use a clock with a lower frequency (let's say 16.6 MHz) or change the duty cycle of a clock to keep more time between the rising edge and falling edge of a clock. This change is just for reading/writing the write shift register, we will use a 33 MHz clock for the analog readout in any case.
If we change like above, are there any concerns from the DRS4 side?

Best,
Seiya

Stefan Ritt wrote:

Dear Seiya,

1) That's correct. SRIN is ampled at the falling edge. Pleae make sure to obey the hold-time as written in the datasheet. P.12, Fig. 11: SRIN must be stable before the falling edge of SRCLK and tH after the falling clock. tH is 5ns according to table 1. 

2) The write shift register is a 8-bit shift register, with an input, output and clock. After the first clock pulse, the 7th bit is shown, after the second clock pulse the 6th bit and so on. You you need 8 clock pulses to read the whole register. At the same time you write to the register, so what ever is present at SRIN will replace the old 8 bits of that register.

3) No this is not possible. When you read the register, you write to it at the same time. One possibilty is to connect SROUT to SRIN during that (maybe via the FPGA). Then you have a circular register wich is the same after each 8 clock pulses.

For your reference, I posted a commercial D-Flip Flop (TI SNHCS72). The DRS4 write shift register is a simple array of 8 such registers, with no CLR or PRE, where SROUT is Q of the last Flip Flop.

Best,
Stefan

Seiya Nozaki wrote:

Dear Stefan,

I have questions about the timing diagram of SROUT/SRIN signal to write/read a write shift register.
1) Value of SRIN signal is saved at the falling edge of SRCLK, correct? (It is written in datasheet, page12, "Bits are latched into the shift register on the falling edge of SRCLK")
2) When are 8-bits of write shift register shown through SROUT? At ridging edges of SRCLK? and with additional delay(~10ns)? or falling edges?
3) In my understanding, when SRCLK is sent to DRS4, we can read and write the values in parallel, right? If so, is it possible just to read the registers without updating the registers?

[Background]
We have two modes to set the write shift register, the first one is to always reconnect to the first line and another one is to reconnect to the same line as when DWRITE goes to Low.
We can read/write the write shift register with the first mode (channel reset, page1). But we rarely face the problem of write shift register, unexpected values are written, with the second mode. With this mode, SROUT signal is sent back to DRS from FPGA as SRIN to write the same value on the write shift register. So there is a small delay(~10ns) due to the routing (DRS->FPGA->DRS, page2). It seems SRIN signal is not stable around the falling edges of SRCLK, thus it could cause that unexpected values are written in write shifter register.
To understand the situation clearly, I'd like to know the answer to the above questions.

Thank you.

Best regards,
Seiya

 

 

 

  804   Wed Oct 28 04:32:19 2020 Seiya NozakiTiming diagram of SROUT/SRIN signal to write/read a write shift register

Dear Stefan,

OK, it's good to hear! Thank you!

Best,
Seiya

Stefan Ritt wrote:

This is a static shift register, so you can make the clock as slow as you want. Actually I don't use a "clock", I just use a data pin I control via a state machine in the VHDL code. This way I have more control over the edges. I need several (internal) clock cycles to produce one SRCLK clock cycle, but that does not matter for the DRS.

Stefan

Seiya Nozaki wrote:

Dear Stefan,

Thank you for your reply.
SRIN is directly connected to SROUT via FPGA for now, but it is unstable for the timing between clock and SRIN depending on the firmware logic.
We want to make our system more robust, so we are thinking to use a clock with a lower frequency (let's say 16.6 MHz) or change the duty cycle of a clock to keep more time between the rising edge and falling edge of a clock. This change is just for reading/writing the write shift register, we will use a 33 MHz clock for the analog readout in any case.
If we change like above, are there any concerns from the DRS4 side?

Best,
Seiya

Stefan Ritt wrote:

Dear Seiya,

1) That's correct. SRIN is ampled at the falling edge. Pleae make sure to obey the hold-time as written in the datasheet. P.12, Fig. 11: SRIN must be stable before the falling edge of SRCLK and tH after the falling clock. tH is 5ns according to table 1. 

2) The write shift register is a 8-bit shift register, with an input, output and clock. After the first clock pulse, the 7th bit is shown, after the second clock pulse the 6th bit and so on. You you need 8 clock pulses to read the whole register. At the same time you write to the register, so what ever is present at SRIN will replace the old 8 bits of that register.

3) No this is not possible. When you read the register, you write to it at the same time. One possibilty is to connect SROUT to SRIN during that (maybe via the FPGA). Then you have a circular register wich is the same after each 8 clock pulses.

For your reference, I posted a commercial D-Flip Flop (TI SNHCS72). The DRS4 write shift register is a simple array of 8 such registers, with no CLR or PRE, where SROUT is Q of the last Flip Flop.

Best,
Stefan

Seiya Nozaki wrote:

Dear Stefan,

I have questions about the timing diagram of SROUT/SRIN signal to write/read a write shift register.
1) Value of SRIN signal is saved at the falling edge of SRCLK, correct? (It is written in datasheet, page12, "Bits are latched into the shift register on the falling edge of SRCLK")
2) When are 8-bits of write shift register shown through SROUT? At ridging edges of SRCLK? and with additional delay(~10ns)? or falling edges?
3) In my understanding, when SRCLK is sent to DRS4, we can read and write the values in parallel, right? If so, is it possible just to read the registers without updating the registers?

[Background]
We have two modes to set the write shift register, the first one is to always reconnect to the first line and another one is to reconnect to the same line as when DWRITE goes to Low.
We can read/write the write shift register with the first mode (channel reset, page1). But we rarely face the problem of write shift register, unexpected values are written, with the second mode. With this mode, SROUT signal is sent back to DRS from FPGA as SRIN to write the same value on the write shift register. So there is a small delay(~10ns) due to the routing (DRS->FPGA->DRS, page2). It seems SRIN signal is not stable around the falling edges of SRCLK, thus it could cause that unexpected values are written in write shifter register.
To understand the situation clearly, I'd like to know the answer to the above questions.

Thank you.

Best regards,
Seiya

 

 

 

 

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