 Thu Apr 13 16:50:18 2017, Stefan Ritt, Stand-alone Time Calibration for PSI Board
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Hard to say. Timing calibration is quite delicate. If you start from scratch, better read this paper: https://arxiv.org/abs/1405.4975
If you try to extract the code from DRS.cpp, better read the paper, too. Probably it will not be possible to develop or extract the code without
knowing how it works. |
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Thu Apr 13 16:54:32 2017, Christian Farina, Stand-alone Time Calibration for PSI Board
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Hi Stefan,
Thank you for your reply. I have read the paper already. I looked through the code and I understand that the LTC and GTC are performed by the
AnalyzeSlope and AnalyzePeriod functions, respectively, correct? It seems to me to be a complicated business to re-write that part from scratch, at least |
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Thu Apr 13 17:02:01 2017, Stefan Ritt, Stand-alone Time Calibration for PSI Board
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Than you can try to isolate the code. Note that different SCAs might work differently. Like the DRS4 has a channel-to-channel jitter which others might
not. But you will see.
Stefan |
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Thu Apr 13 17:10:58 2017, Christian Farina, Stand-alone Time Calibration for PSI Board
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Thank you for your help Stefan. I will try to get the TC part isolated.
Stefan
Ritt wrote:
Than you can try to isolate the code. Note that different SCAs might |
 Fri Apr 9 20:29:45 2021, Sean Quinn, Spikes/noise sensitive to clock settings? 
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Dear DRS4 team,
I'm trying to troubleshoot some odd spike behavior. If I run the ADC and SR CLK at 16 MHz (behavior also seen at 33 MHz) we get very noisy
data (post-calibration) with periodic spikes. |
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Fri Apr 9 21:38:59 2021, Stefan Ritt, Spikes/noise sensitive to clock settings?
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elog:824
Sean
Quinn wrote:
Dear DRS4 team, |
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Fri Jun 24 09:57:36 2022, LynseyShun, Spikes/noise sensitive to clock settings?
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Hello, I now have periodic spikes in CH0 and CH1 output. How can I eliminate these spikes? I'm sorry I didn't understand your elimination
method. Please explain the method in detail. Thank you very much
Stefan |
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Fri Jul 29 17:23:43 2022, Stefan Ritt, Spikes/noise sensitive to clock settings?
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Look at the DRS4 data sheet, Figure 12. You see there the rising SRCLK pulse which outputs the next analog value. You also see tSAMP which describes
the sampling piont (strobe or clock sent to your ADC). The value of tSAMP must be such that the values is sampled at the point where it flattens out, just
2-3 ns BEFORE the next analog sample is clocked out, as written in the text. So you have to phase shift your clock going to SRCLK and the one going to |
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Tue May 27 13:46:18 2014, Dominik Neise, Spikes in DRS4 data on custom baord.
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We see quite some spikes in our DRS4 sampled data in FACT. We see different types of spikes:
single cell spikes, usually showing a large amplitude of 200mV
double cell spikes, usually only in the order of 20mV.
Even triple and quadro cell spikes are rarely seen.
The double cell spikes often occur as symmetrical double cell spikes mirrored |
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Tue May 27 16:07:17 2014, Stefan Ritt, Spikes in DRS4 data on custom baord.
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Dominik Neise wrote:
We see quite some spikes in our DRS4 sampled data in FACT. We see different types of spikes: |
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Wed Aug 28 13:07:51 2013, Andrey Kuznetsov, Some bug fixes and questions
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For http://www.psi.ch/drs/DocumentationEN/manual_rev20.pdf:
0 0x02 15..8 board_type 5 for DRS4 USB Evaluation Board 1.1 ---> should instead say Evaluation Board 2.0 ?
I've been reviewing DRS.cpp v4.0.1 |
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Thu Sep 5 10:01:00 2013, Andrey Kuznetsov, Some bug fixes and questions
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#11 0x080589de in DRSBoard::GetWave (this=0xb7456008, chipIndex=0, channel=0 '\000', waveform=0x40f24000, responseCalib=true, triggerCell=207, wsr=0,
adjustToClock=false, threshold=1, offsetCalib=true) at src/DRS.cpp:3380
This is calling: |
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Mon Sep 9 06:49:36 2013, Andrey Kuznetsov, Some bug fixes and questions
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| The DRSCallback *pcb is missing an if statement in the code when DRS Oscilloscope software isn't used when calibrating in function: int DRSBoard::CalibrateTiming(DRSCallback *pcb) |
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Wed Jan 15 16:15:00 2014, Stefan Ritt, Some bug fixes and questions
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Andrey Kuznetsov wrote:
For http://www.psi.ch/drs/DocumentationEN/manual_rev20.pdf: |
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Wed Jan 15 17:02:58 2014, Stefan Ritt, Some bug fixes and questions
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Andrey Kuznetsov wrote:
So although it doesn't affect data retrieval, it's just dumb luck the function ends up being called |
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Wed Jan 15 17:11:14 2014, Stefan Ritt, Some bug fixes and questions
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Andrey Kuznetsov wrote:
The DRSCallback *pcb is missing an if statement in the code when DRS Oscilloscope software |
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Wed Mar 5 21:54:13 2014, Hermann-Josef Mathes, Software drs-5.0.0 fails to compile (drsosc)
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Hi,
the latest software drs-5.0.0.tar.gz fails to compile on my freshly installed SuSE 13.1 whereas the previous 4.0.1 is compiling out-of-the-box.
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Thu Mar 6 11:12:44 2014, Stefan Ritt, Software drs-5.0.0 fails to compile (drsosc)
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Hermann-Josef Mathes wrote:
Hi, |
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Wed Feb 16 14:06:45 2022, Dmitry Hits, Sliders missing in drsosc
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Hi everyone,
Did anyone have a "missing sliders problem" in GUI (see attachment) accompanied by the following message in the terminal.
(drsosc:4611): Gtk-WARNING **: 14:05:11.249: Negative content width -4 (allocation 20, extents 12x12) while allocating gadget (node scale, owner |
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Thu Feb 22 01:21:11 2024, Rod McInnis, Simulation of FPGA
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Hello:
A bit of background: I am working on a project that is utilizing the DRS4 Evaluation board as a prototype platform for a dedicated, special
use capture. We will only be utilizing one channel of the ADC capture, and the 1024 samples is more than enough. |