Dear Mr. S. Ritt

       i am Ms. student , am working with your DRS4 board to calculate the time of flight of the cosmic particle which passes trough  the hodoscope . i see the signals at scope , which is negative (i don't want to take positive side of the signal).

       i am using your drs_exap.cpp file to  take the data, i set the analog trigger source , threshold level is negative, like this(b->SetTriggerLevel(-30, true) ); but the exam file also registers the positive side of signal (i think  that is spike or internal reflection), is it possible to eliminate this spike? Also i want to register  the data just after the threshold value, but that is always triggered, i think that caused from the mode. Is it possible to set the trigger mode to normal in exam file?,and  how can i do that?

Best regards.

Sincerely,

 Ali YILMAZ (ali.yilmaz@roma1.infn.it)

Please note that SetTriggerLevel(level, polarity) needs "level" in volts, not millivolts, so you need SetTriggerLevel(-0.3, true). The trigger mode is not specified with any library call, but depends on what your program does. If you always poll on IsBusy(), then you are already in "normal" mode. The auto mode can only be achieved on the user application level by doing an "artifical" trigger by calling SoftTrigger() if there are no hardware triggers for a certain time. 

                                                                                                            Fig.1        typical dimension of QFN package

Above is the typical dimension specification for QFN package. I cann't find the corresponding "T1" as in Fig.1 in the DRS4 documents, nor any of the tolerance of the dimensions, which are usually expressed in the form of  a range between a min. value and a max. value.

So will you specify the dimension of "T1" and "W1", and the dimension tolerance of them?

Thanks and best wishes!

                                                                               Jinhong Wang       University of Science and Technology of China

Please find attached the complete dimensions.

No. It shifts about ROFS-0.25V. So only if ROFS=1.55V, the shift will be 1.3V.

Just read the datasheet under "ANALOG OUTPUTS". I'm sorry if I did not describe this clearly, but the U+ voltage is fixed (only dependent on ROFS), and U- can be calculated using Uofs as written in the datasheet. 

OUT+ is 0.8V~1.8V, OUT- is 2*Uofs-OUT+. So you can only change the OUT- level, not the OUT+ level. 

Hi! Stefan:

  when I change a new computer(win7,64bit),I meet a problem that the drscl app cannot found the board! It shows"USB successfully scanned,but no boards found",but the drsosc runs well . when I connect to other win7*64bits computer,only one of them runs property! Is there any driver else I need to install? 

Thank you!

Chen

This problem has been reported by several people, like elog:551

So far I could not solve it. On the computers at our lab it works find so I cannot reproduce and fix the problem. One suspicion I have is that the underlying libusb library needs to be updated. You can try to install the newest version from their website at http://libusb.info/, but I haven't tried it myself.

Stefan

I have tried about 4 computers,only one worked fine.I truly want to know how others get this fixed,can you get in touch with them?

Hi

I want to use DRS4 to digitize 16 channels of signals. The width of signal is about 20 ns, with frequency of 50Hz. The time differences between these 16 signals are not constant, arranging from 3us to 0. I am confused about this in some aspects.

1. Can I use SIMULTANEOUS WRITINT AND READING to realize this? I saw the VHDL program, and if I understand it correctly, it did not work at this state.
2. Or sampling at 1GSPS, using CASCADING OF CHANNELS, I can sample signal at most 4us or 8us, then digitizing all signals of one chip. Have you tested 4 or more channels cascading before?

Besides, any advice will be helpful!

Thank you.

Hi

I want to use DRS4 to digitize 16 channels of signals. The width of signal is about 20 ns, with frequency of 50Hz. The time differences between these 16 signals are not constant, arranging from 3us to 0. I am confused about this in some aspects.

1. Can I use SIMULTANEOUS WRITINT AND READING to realize this? I saw the VHDL program, and if I understand it correctly, it did not work at this state.
2. Or sampling at 1GSPS, using CASCADING OF CHANNELS, I can sample signal at most 4us or 8us, then digitizing all signals of one chip. Have you tested 4 or more channels cascading before?

Besides, any advice will be helpful!

Thank you.

1. Simultaneous writing and reading is not possible with the DRS4 chip. The manual says differently on p. 14, but due to a bug in the chip waveforms get clipped at the end if one does that. We hopt to fix this problem in a future version of the chip.

2. You can cascade 2,4 or 8 channels. If you cascade 8 channels and run at 1 GSPS, you digitize a window of 8 us. If you have 16 signals, you then need 16 chips.

/Stefan

Hello Stefan,

some colleages told me a story, I was neither able to confirm nor find anything in the datsheet about. According to them:

For some internal reason of the DRS4, if the “stop capacitor” of the DRS4 is >= 767, the true stop channel is one before the stop channel read from the DRS4. In other words, the stop channel which returns the DRS4 shifts after sampling to the capacitor ID 766.

Can you confirm that, or even say a few words about that matter?

I wanted to confirm this by plotting the stop cell distribution for random triggered data, taken with one of the FACT boards. I assumed (possibly misunderstanding the matter), that this would lead to missing values in the area of stop cell 767, but cannot see any significant excess or lack of entries in that area.

I cannot confirm the story with the "stop capacitor > 767". It can be seen from your plots that the distribution of stop cells are even, no holes or bins with double height.

There is an issue with cell 767, but this is when one tries to do simultaneous reading/writing to the chip. This does not really work as writen in the data sheet. Waveforms sometimgs get cut off at cell 767. But the stop cell is always correct, otherwise one could not calibrate the data. If you use the evaluation board for example, which is perfectly calibrated, and introduce an "artifical" shift like

if stop cell > 767 then
  stop cell = stop cell + 1

then you would see that the voltage calibration would become wrong and very noisy.

Stefan

Hi,

I have been collecting some date using the DRS4 board at a trigger rate of 10-20 Hz,    I only need the timestamp and the amplitude, is there anyway to select only these two live as the data comes in to be stored. 

Alternatively,  What's the maximum file size or maximum number of events I can store in one binary file in linux. 

Thanks,

Best,

Abaz

The maximum file size depends on the underlying linux file system. Common values are 4-16 GBytes.

Stefan

Dear Stefan

Is there an easy way to reduce sampling speed below 0.7 GSPS? I would like to record traces up to 5 usec long.

Thank you

Dmitry 

No. See the DRS4 datasheet: http://www.psi.ch/drs/DocumentationEN/DRS4_rev09.pdf 

Minimum sampling speed is 700 MSPS.

/Stefan

Dear all,

I'm using 3 DRS boards simultaneously and their serial numbers are 2169, 2170, 2172 respectively.

Recently however,  I obtain serial number "0" by DRSBoard::GetBoardSerialNumber() for #2172 board.

Data taking can be done without any problems, but I'd like to know what is happening.

Any advice？

Thank you.

Toshihiro Nonaka

If dis- and reconnecting the board does not help, there is the (small) chance that the serial number got erased in the board. You can re-set it with the "drscl" command line tool:

$ drscl
Found DRS4 board 0 on USB, serial #0, firmware revision 21305
B0> serial 2172