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Entry  Sat Feb 20 01:56:05 2010, Hao Huan, PLLLCK signal of DRS4 
    Reply  Sat Feb 20 09:54:48 2010, Stefan Ritt, PLLLCK signal of DRS4 start_1ghz.png
       Reply  Sun Feb 21 00:46:01 2010, Hao Huan, PLLLCK signal of DRS4 
          Reply  Sun Feb 21 13:47:03 2010, Stefan Ritt, PLLLCK signal of DRS4 
             Reply  Sun Feb 21 20:27:46 2010, Hao Huan, PLLLCK signal of DRS4 
                Reply  Sun Feb 21 20:33:57 2010, Stefan Ritt, PLLLCK signal of DRS4 
                   Reply  Mon Feb 22 17:23:59 2010, Hao Huan, PLLLCK signal of DRS4 
                      Reply  Wed Mar 3 14:37:40 2010, Stefan Ritt, PLLLCK signal of DRS4 
Message ID: 41     Entry time: Sun Feb 21 13:47:03 2010     In reply to: 39     Reply to this: 42
Author: Stefan Ritt 
Subject: PLLLCK signal of DRS4 

Hao Huan wrote:


Thanks! I see. The capacitor is important. However I'm a little confused... If PLLLCK=DTAP XOR REFCLK, shouldn't it integrate to low instead of high when the two clocks are in phase? I must have some misunderstanding here. So if we ignore any realistic complexity and assume DTAP is perfectly locked with REFCLK, will PLLLCK be always low or high? I'm sorry I do not know how the DRS internal PLL and its input/output work...

Actually the XOR is followed by an inverter, so it will integrate to high if the two clocks are in phase. 

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