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Entry  Sat Feb 20 01:56:05 2010, Hao Huan, PLLLCK signal of DRS4 
    Reply  Sat Feb 20 09:54:48 2010, Stefan Ritt, PLLLCK signal of DRS4 start_1ghz.png
       Reply  Sun Feb 21 00:46:01 2010, Hao Huan, PLLLCK signal of DRS4 
          Reply  Sun Feb 21 13:47:03 2010, Stefan Ritt, PLLLCK signal of DRS4 
             Reply  Sun Feb 21 20:27:46 2010, Hao Huan, PLLLCK signal of DRS4 
                Reply  Sun Feb 21 20:33:57 2010, Stefan Ritt, PLLLCK signal of DRS4 
                   Reply  Mon Feb 22 17:23:59 2010, Hao Huan, PLLLCK signal of DRS4 
                      Reply  Wed Mar 3 14:37:40 2010, Stefan Ritt, PLLLCK signal of DRS4 
Message ID: 43     Entry time: Sun Feb 21 20:33:57 2010     In reply to: 42     Reply to this: 44
Author: Stefan Ritt 
Subject: PLLLCK signal of DRS4 

Hao Huan wrote:

By the way I have another question: when the default operation mode of the DRS4 chip is used, i.e. WSRIN is fed internally to WSROUT, at the external pins is it necessary to leave the WSRIN open? Or any input through the pin will not affect the Domino wave running? Also I observe that WSROUT will be always low when the chip is running in this mode; is it the supposed behavior?

If the WSRin is fed internally to WSROUT, then the level of the WSRIN pin does not matter, it's just disconnected. You can leave the pin open without problem. WSROUT is however active, so you can observe the internal state of the write shift register. In the default configuration (8x1024 sampling cells), all 8 channels are active all the time, so the WSR is loaded with ones. The inverter at the output then makes all zeros from this. If you configure the chip as 4x2048 cells, then you will observe switching bits at WSROUT. 

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