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DRS4 Forum
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| DRS4 Discussion Forum |
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 Sat Feb 20 01:56:05 2010, Hao Huan, PLLLCK signal of DRS4
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 Sat Feb 20 09:54:48 2010, Stefan Ritt, PLLLCK signal of DRS4 
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Sun Feb 21 00:46:01 2010, Hao Huan, PLLLCK signal of DRS4
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Sun Feb 21 13:47:03 2010, Stefan Ritt, PLLLCK signal of DRS4
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Sun Feb 21 20:27:46 2010, Hao Huan, PLLLCK signal of DRS4
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Sun Feb 21 20:33:57 2010, Stefan Ritt, PLLLCK signal of DRS4
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Mon Feb 22 17:23:59 2010, Hao Huan, PLLLCK signal of DRS4
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Wed Mar 3 14:37:40 2010, Stefan Ritt, PLLLCK signal of DRS4
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Message ID: 42
Entry time: Sun Feb 21 20:27:46 2010
In reply to: 41
Reply to this: 43
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| Author: |
Hao Huan |
| Subject: |
PLLLCK signal of DRS4 |
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| Stefan Ritt wrote: |
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| Hao Huan wrote: |
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Thanks! I see. The capacitor is important. However I'm a little confused... If PLLLCK=DTAP XOR REFCLK, shouldn't it integrate to low instead of high when the two clocks are in phase? I must have some misunderstanding here. So if we ignore any realistic complexity and assume DTAP is perfectly locked with REFCLK, will PLLLCK be always low or high? I'm sorry I do not know how the DRS internal PLL and its input/output work...
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Actually the XOR is followed by an inverter, so it will integrate to high if the two clocks are in phase.
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Got it. Thank you! By the way I have another question: when the default operation mode of the DRS4 chip is used, i.e. WSRIN is fed internally to WSROUT, at the external pins is it necessary to leave the WSRIN open? Or any input through the pin will not affect the Domino wave running? Also I observe that WSROUT will be always low when the chip is running in this mode; is it the supposed behavior? |