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Entry  Sun May 2 18:36:14 2010, Ignacio Diéguez Estremera, DRS4 chip model 
    Reply  Mon May 3 11:09:12 2010, Stefan Ritt, DRS4 chip model 
       Reply  Mon May 3 17:06:02 2010, Ignacio Diéguez Estremera, DRS4 chip model 
          Reply  Mon May 3 17:10:29 2010, Stefan Ritt, DRS4 chip model 
             Reply  Mon May 3 23:21:55 2010, Ignacio Diéguez Estremera, DRS4 chip model 
                Reply  Tue May 4 11:26:21 2010, Stefan Ritt, DRS4 chip model DRS4_S-Parameter.pdf
                   Reply  Tue May 4 16:23:16 2010, Ignacio Diéguez Estremera, DRS4 chip model 
                   Reply  Wed May 12 11:47:39 2010, Jinhong Wang, DRS4 chip model 
                      Reply  Wed May 12 16:26:12 2010, Stefan Ritt, DRS4 chip model 
Message ID: 69     Entry time: Sun May 2 18:36:14 2010     Reply to this: 70
Author: Ignacio Diéguez Estremera 
Subject: DRS4 chip model 

Hi all,

i'm an electronics engineering student at UCM (Madrid) working on my master's thesis within the CTA collaboration. I'm designing the readout electronics for the telescope's camera, and i'm focusing in using GAPDs instead of PMTs and using the domino chip for the sampling of the signal. I was wondering if there is a spice and/or RF model of the DRS4 chip available. It would be very useful to perform some simulations before deciding to use the chip as the sampling solution for our prototypes.

If the answer is negative, can you give me some advise for modelling the chip in spice? Have you done any simulations?

Thanks in advance,

Ignacio Diéguez Estremera.

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