So i guess i won't be able to include drs4 in my simulations :-(. Any other suggestions? Maybe the S-params model you where working on? Anything is better than nothing :-)
Please find attached the S-parameters.
Hi, we plan to do a time interpolating among the eight channels on a single chip to obtain a maximum 40 GSPS (or, maybe 30 GSPS ) sampling rate. Hence RF behavior of the anlog input is very important for us.
Will you give us some advice on the modeling of the anlog input circuit of the chip? Perhaps just the Spice model of the analog input?
The attached S parameters I found here is for fs =1 GSPS, what about fs=5GSPS?
thanks in advance,
Jinhong Wang (firstname.lastname@example.org ; email@example.com)