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Entry  Sun May 2 18:36:14 2010, Ignacio Diéguez Estremera, DRS4 chip model 
    Reply  Mon May 3 11:09:12 2010, Stefan Ritt, DRS4 chip model 
       Reply  Mon May 3 17:06:02 2010, Ignacio Diéguez Estremera, DRS4 chip model 
          Reply  Mon May 3 17:10:29 2010, Stefan Ritt, DRS4 chip model 
             Reply  Mon May 3 23:21:55 2010, Ignacio Diéguez Estremera, DRS4 chip model 
                Reply  Tue May 4 11:26:21 2010, Stefan Ritt, DRS4 chip model DRS4_S-Parameter.pdf
                   Reply  Tue May 4 16:23:16 2010, Ignacio Diéguez Estremera, DRS4 chip model 
                   Reply  Wed May 12 11:47:39 2010, Jinhong Wang, DRS4 chip model 
                      Reply  Wed May 12 16:26:12 2010, Stefan Ritt, DRS4 chip model 
Message ID: 72     Entry time: Mon May 3 17:10:29 2010     In reply to: 71     Reply to this: 73
Author: Stefan Ritt 
Subject: DRS4 chip model 

Ignacio Diéguez Estremera wrote:

Stefan Ritt wrote:

Ignacio Diéguez Estremera wrote:

Hi all,

i'm an electronics engineering student at UCM (Madrid) working on my master's thesis within the CTA collaboration. I'm designing the readout electronics for the telescope's camera, and i'm focusing in using GAPDs instead of PMTs and using the domino chip for the sampling of the signal. I was wondering if there is a spice and/or RF model of the DRS4 chip available. It would be very useful to perform some simulations before deciding to use the chip as the sampling solution for our prototypes.

If the answer is negative, can you give me some advise for modelling the chip in spice? Have you done any simulations?

Thanks in advance,

Ignacio Diéguez Estremera.

Yes there is a transistor-level spice model, which I used to design the chip, but you won't be happy with it: Given the 500,000+ transistors on the chip, a 100 ns simulation takes a couple of weeks. We tried to make a simplified model just for the analog input using some measured S-parameters, but found that the RF behavior of the chip is almost impossible to describe to better than let's say 50%. In the end you have to fine-tune your analog front-end experimentally, to obtain optimal bandwidth. We are just working on a reference design with gives you 850 MHz bandwidth using an active input buffer.

 Thanks for the information.

I would like to try the huge :-) model. Can you send it to my email address? Since the input signal are pulses of a few nanoseconds at FHWM, the simulation time may be reduced. I will post some feedback in the forum once i give it a try.

Kind regards.

I just checked and realized that we are not allowed to give out the "huge" model since it contains parameters from the chip manufacturer's library which are confidentially. 

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