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ID Date Author Subject Text Attachments
  835   Sat Sep 18 15:48:30 2021 Stefan Rittdrs_exam_multi with non-v4 boards, default configurationHi,

please note the the evaluation
board is what it says, a board to evaluate
  
  834   Sat Sep 18 15:47:50 2021 Stefan Ritthow to acquire the stop channel with 2x4096 cascading The problem must be on your side, since
the Write Shift Register readout works in
other applications with the DRS4 chip. So
  
  833   Thu Sep 16 19:04:06 2021 Patrick Moriishi Freemandrs_exam_multi with non-v4 boards, default configurationHello, 

I made a modified version drs_exam_multi.cpp,
but ran into an issue when running.  When
  
  832   Mon Sep 6 14:42:23 2021 Jiaolonghow to acquire the stop channel with 2x4096 cascading Hi Steffan,

    I have a question
about how to acquire the stop channel: 
  
  831   Tue Aug 10 13:57:09 2021 Mehrpad MonajemC code to read the 4 channel with external triggerThank you for the reply.

In the version that I have, I cannot
find drs_exam_2048.cpp file. Could you please
  
  830   Mon Aug 9 12:50:31 2021 Stefan RittC code to read the 4 channel with external triggerSorry the late reply, I was on vacation. 

Here are some answers:

1. I'm sorry I can't help
  
  829   Wed Jul 14 14:55:09 2021 Mehrpad MonajemC code to read the 4 channel with external triggerHi there,

Recently I bought a 5GSPS evaluation
board with 2048 sampling points.
  
  828   Wed May 5 10:12:44 2021 Stefan Rittrecording only timestamp and amplitude and/or filesize maximumThe maximum file size depends on the underlying
linux file system. Common values are 4-16
GBytes.
  
  827   Tue May 4 21:18:28 2021 Abaz Kryemadhirecording only timestamp and amplitude and/or filesize maximumHi,

I have been collecting some date
using the DRS4 board at a trigger rate of
  
  826   Fri Apr 9 21:56:54 2021 Sean QuinnUnexpected noise in muxout: t_samp related?Yes, there is some systematic board noise
on this prototype, unfortunately 
  
  825   Fri Apr 9 21:38:59 2021 Stefan RittSpikes/noise sensitive to clock settings?elog:824




  
  824   Fri Apr 9 20:55:28 2021 Stefan RittUnexpected noise in muxout: t_samp related?If you do the cell calibration correctly,
your noise should be ~0.4 mV. You seem to
be 2-3x larger. The periodic negative spikes
  
  823   Fri Apr 9 20:29:45 2021 Sean QuinnSpikes/noise sensitive to clock settings?Dear DRS4 team,

I'm trying to troubleshoot
some odd spike behavior. If I run the ADC
 spikes_16MHz.pngspike_period.pngbetter_spikes_15MHz.pngspike_period_15MHz.png 
  822   Fri Apr 9 20:22:13 2021 Sean QuinnUnexpected noise in muxout: t_samp related?Hi Stefan,

 

Thanks much for the quick reply.
 ex_cal_wave.png 
  821   Wed Apr 7 08:26:12 2021 Stefan RittUnexpected noise in muxout: t_samp related?Dear Sean,

noise in transparent mode comes
from some coupling to your system clock.
  
  820   Wed Apr 7 03:29:39 2021 Sean QuinnUnexpected noise in muxout: t_samp related?Dear DRS4 team,

I'm experiencing some issues
that seem to be isolated to the ASIC, and
 transp_example.PNGtransp_readout_example_noise.PNGdrs_datasheet_fig11.PNGr0_r1_delay.png 
  819   Fri Mar 5 09:39:42 2021 Stefan RittTrouble getting PLL to lockThat probably depends on the way your FPGA
boots. If the SRCLK signal goes high after
the SRIN - even a few ns - you might clock
  
  818   Thu Mar 4 21:36:14 2021 Tom SchneiderTrouble getting PLL to lockI found the problem, and it had nothing
to do with the CMOS clock input.  As
it turns out, even though I was using the
  
  817   Fri Feb 26 22:52:13 2021 Tom SchneiderTrouble getting PLL to lockThats not a simple modification to my PCB,
but I'll give it a try.  Thanks
for your help
  
  816   Fri Feb 26 22:12:58 2021 Stefan RittTrouble getting PLL to lockSounds to me like your REFCLK is not getting
through or your PLL loop is open. Could be
a bad solder connection. Try to measure signals
  
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