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New entries since:Thu Jan 1 01:00:00 1970
ID Date Author Subject Text Attachments
  791   Tue May 26 12:44:16 2020 Stefan RittDomino waveLook at the attached picture. For simplicity,
only 4 cells are open and tracking the input
signal. Time is flowing from top to bottom.
 Screenshot_2020-05-26_at_12.43.40_.png 
  790   Tue May 26 11:10:27 2020 xgggDomino waveHi Stefan,

According to the datasheet DRS_rev09,
the write signal is always 16 cells wide.
  
  789   Mon May 25 03:36:12 2020 Keita MizukoshiDRS4 Evaluation board control tool 'drscl' with macro fileThank you very much. That is what I wanted.




  
  788   Fri May 22 13:24:51 2020 Stefan RittType check at DOFrame.h in official softwareThe software is a bit outdated, I will
soon make a new release. 

In meantime, you can replace that
  
  786   Fri May 22 12:53:33 2020 Stefan RittDRS4 Evaluation board control tool 'drscl' with macro fileThere is an example program in the distribution
under software/drscl/drs_exam.cpp which is
a stand-alone program to do what you need.
  
  785   Thu May 21 07:38:05 2020 Keita MizukoshiType check at DOFrame.h in official softwareHi,

 

I've failured to compile official
  
  784   Thu May 21 07:18:48 2020 Keita MizukoshiDRS4 Evaluation board control tool 'drscl' with macro fileDear experts,

 

I would like to use DRS4 evaluation
  
  783   Mon Mar 23 15:03:28 2020 Ajay KrishnamurthyUSB trigger issueHello,

I had forgotten to disable the
turn off the power to the USB drive on Windows
  
  782   Fri Oct 25 16:39:07 2019 Stefan RittComputing corrected time from binary data...what is t_0,0?t0,0 refers to the time of cell #0 of channel
#0. So basically you keep channel 0 fixed,
calculate the difference of each channel's
  
  781   Wed Oct 23 17:56:26 2019 John JendzurskiComputing corrected time from binary data...what is t_0,0?In the equations for computing the corrected
time for channels other than channel 1, does
anyone know what the term t0,0 refers
 Screenshot.png 
  780   Tue Oct 15 08:14:17 2019 Danyanghow to acquire the stop position with channel cascadingThanks a lot. The problem is solved when
A3-A0 is set 1101 and srclk keeps low.

Best Regards,
  
  779   Mon Oct 14 15:27:09 2019 Stefan Ritthow to acquire the stop position with channel cascadingIf you configure the Write Shift Register
with 01010101b, then all you have to do after
a trigger is to set A3-A0 to 1101. The WSROUT
  
  778   Mon Oct 14 13:44:26 2019 Danyanghow to acquire the stop position with channel cascadingYes, firstly I configured the chip
with 4x2048 bins by setting the Write Shift
Register to 01010101b, A3-A0
  
  777   Mon Oct 14 12:56:13 2019 Stefan Ritthow to acquire the stop position with channel cascadingNote that you have to read out the Write
Shift Register only if you do channel cascading,
e.g. configuring the chip with 4x2048 bins
  
  776   Mon Oct 14 11:45:06 2019 Danyanghow to acquire the stop position with channel cascadingI tried the
logic in my designed board.  The results
are shown in the picture: Srout keeps low
 Capture.PNG 
  775   Mon Oct 14 10:14:46 2019 Stefan Ritthow to acquire the stop position with channel cascadingYou first set A3-A0, on the next clock
cycle you issue pulses on srclk, and about
10ns after each clock pulse the output shows
  
  774   Mon Oct 14 09:32:33 2019 Danyanghow to acquire the stop position with channel cascadingHi Steffan,

       In DSR4
DATASHEET Rev.0.9 Page13,  there is
 Capture.PNG 
  773   Fri Sep 13 15:27:41 2019 Arseny RybnikovScaler / How to modify the firmware to change the scaler integration timeHello,

We want to use the inner DRS4 counter(scaler)
within more than the 100ms integration
  
  772   Tue Aug 27 09:14:03 2019 Stefan RittDRS4Is a 5 GSPS oscilloscope suitable for use
with Silicon surface barier detectors?

  
  771   Tue Aug 27 08:33:22 2019 chinmay basuDRS4Is DRS4 suitable for use with Silicon surface
barrier detectors?
  
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