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ID Date Author Subject Text Attachments
  552   Fri Oct 28 15:51:59 2016 Stefan RittProblems with DRS command lineNo, I absolutely have no idea. Both DRSOsc
and drscl use exaclty the same code to access
USB.
  
  551   Fri Oct 28 15:02:18 2016 Simon MendischProblems with DRS command line[quote="Stefan Ritt"]
You are the first one describing this problem
(out of ~200 people), so I guess the problem
  
  550   Thu Oct 27 08:29:26 2016 Stefan RittProblems with DRS command line[quote="Alexey Lubinets"]Hello, everybody

I have installed the software for the DRS4
  
  549   Wed Oct 26 21:15:35 2016 Alexey LubinetsProblems with DRS command lineHello, everybody

I have installed the software for the DRS4
  
  548   Tue Oct 11 22:11:26 2016 Stefan Ritttime difference between 2 channels only ~30-35ps @ 5GSmples/sThank you very much! I will check it tomorrow!

-d

Concerning the offset, it looks
  
  547   Tue Oct 11 09:20:04 2016 Stefan Ritttime difference between 2 channels only ~30-35ps @ 5GSmples/sConcerning the offset, it looks to me like
you moved the offset slider slider of channel
1 to a non-zero position. You see that from
  
  546   Tue Oct 11 09:04:33 2016 Danny Petschketime difference between 2 channels only ~30-35ps @ 5GSmples/sHello Stefan,

thanks for the paper. That makes
sense. I thought about sth. like that but
  
  545   Mon Oct 10 12:03:27 2016 Stefan Ritttime difference between 2 channels only ~30-35ps @ 5GSmples/sOk, I got it. The timing resolution is
affected by the signal-to-noise ratio over
the rise-time of your signal. You find the
 Screen_Shot_2016-10-10_at_12.01.03_.pngScreen_Shot_2016-10-10_at_12.01.57_.pngScreen_Shot_2016-10-10_at_12.36.48_.png 
  544   Mon Oct 10 11:30:37 2016 Danny Petschketime difference between 2 channels only ~30-35ps @ 5GSmples/sHello Stefan,

Chn2 & Chn3 were used for delay-determination as
you can see on the second picture.
 allChannels_zero_scaled.pngChn2_Chn3_1ns_delay_scaled.png 
  543   Sun Oct 9 11:39:18 2016 Stefan Ritttime difference between 2 channels only ~30-35ps @ 5GSmples/sCan you post a screenshot of your measurement?

Stefan

  
  542   Sun Oct 9 10:43:35 2016 Danny Petschketime difference between 2 channels only ~30-35ps @ 5GSmples/s(Board Type:9, DRS4)

Hello,

I´m trying to reach the timig
  
  541   Thu Oct 6 15:23:18 2016 Will Flanagan Hi Stefan,

That is exactly what I'm looking
for. Thanks again!
  
  540   Thu Oct 6 11:18:05 2016 Stefan RittTimestamp for each DRS4 waveformIn the mentioned read_binary.cpp file you
have the line where you read the event header

i = fread(&eh, sizeof(eh),
  
  539   Wed Oct 5 22:43:29 2016 Will FlanaganTimestamp for each DRS4 waveformHi DRS4 Experts,

I have been analyzing DRS4 binary
data with scripts based on Stefan's (very
  
  538   Fri Sep 30 17:03:38 2016 Stefan RittOutput Timing DriftingHi Jacob,

you are missing the timing calibration.
Each sampling cell has not the same width.
  
  537   Thu Sep 29 17:26:13 2016 Jacob HwangOutput Timing DriftingHello,

I have designed four DRS4 chips
(36 channels) on my board running at 1GHz
 Output_Drifting.jpg 
  536   Mon Aug 29 12:51:48 2016 Stefan Rittincrement write config register on the fly?The problem is when you change the write
config register from 11111111 to 01111111,
or from 00001111 to 00000111, then the last
  
  535   Mon Aug 29 12:18:49 2016 benjamin legeytincrement write config register on the fly?If I may trouble you for a little more
information, the critical point then is
that there should not be any zeroes in the
  
  534   Mon Aug 29 10:57:33 2016 Stefan Rittincrement write config register on the fly?The issue with "stopping at cell 767"
would also affect this mode of operation.
Furthermore, the DRS4 chip has only 10 bit
  
  533   Mon Aug 29 09:36:34 2016 benjamin legeytincrement write config register on the fly?Hello,

I have a question about using the
write config register to enable/disable sampling
  
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