DRS4 Forum
  DRS4 Discussion Forum, Page 16 of 45  Not logged in ELOG logo
ID Datedown Author Subject Text Attachments
  603   Thu Apr 13 17:02:01 2017 Stefan RittStand-alone Time Calibration for PSI BoardThan you can try to isolate the code. Note
that different SCAs might work differently.
Like the DRS4 has a channel-to-channel jitter
  
  602   Thu Apr 13 16:54:32 2017 Christian FarinaStand-alone Time Calibration for PSI BoardHi Stefan,

Thank you for your reply. I have
read the paper already. I looked through
  
  601   Thu Apr 13 16:50:18 2017 Stefan RittStand-alone Time Calibration for PSI BoardHard to say. Timing calibration is quite
delicate. If you start from scratch, better
read this paper: https://arxiv.org/abs/1405.4975
  
  600   Thu Apr 13 16:42:21 2017 Christian FarinaStand-alone Time Calibration for PSI BoardHello everybody,

I was trying to create a stand-alone
program that would perform a time calibration
  
  599   Tue Apr 11 09:41:44 2017 Stefan Rittdrs4 registers behaviourWhat I do is the following: Have the RESET
input unconnected. When you power up, this
makes an internal reset during the power
  
  598   Tue Apr 11 09:07:33 2017 Giovanni Brunidrs4 registers behaviourThank you Stefan for replying!
I have still the RESET issue in mind:
how would you suggest to reset properly the
  
  597   Mon Apr 10 14:05:17 2017 Stefan Rittdrs4 registers behaviour1. WRITE SHIFT register and CONFIG registers
are initialized to "1" on power
up, but if you want to change that, use A0-A3
  
  596   Mon Apr 10 13:41:41 2017 Giovanni Brunidrs4 registers behaviourHej Stefan! Thank you for your answer!

Just to be sure to have understood
properly:
  
  595   Mon Apr 10 10:50:57 2017 Stefan Rittdrs4 registers behaviourUsing the RESET line to reset registers
is not a good idea since it can have some
bad side-effects. The READ SHIFT register
  
  594   Mon Apr 10 10:48:03 2017 Stefan RittDRS4 eval board v4 coincidence firmware changes for triger for short pulsesYou have to download the package for your
board, which then includes also the correct
firmware for your board. If you have a V4
  
  593   Mon Apr 10 08:50:11 2017 Giovanni Brunidrs4 registers behaviourHej everyone!
I have some questions regarding what
happens to some DRS registers in some scenarios:
  
  592   Wed Apr 5 12:40:16 2017 Martin PetriskaDRS4 eval board v4 coincidence firmware changes for triger for short pulsesI would like to implement fpga firmware
changes for DRS4 eval board v4 to put there
posibility for standard coincidence (for
  
  591   Wed Apr 5 12:28:28 2017 Stefan Rittdrscl doesn't find eval board but drsosc does (Windows 7)Two people report now this problem, while
this works fine at our lab. So I'm puzzled
right now.
 Screen_Shot_2017-04-05_at_12.27.46_.pngScreen_Shot_2017-04-05_at_11.45.07_.png 
  590   Tue Mar 28 21:53:12 2017 Jim Freemandrscl doesn't find eval board but drsosc does (Windows 7)I cannot find the EVAL board using drscl
version 5.06 while the drsosc works fine.
I tried 2 different eval boards and 2 different
  
  589   Fri Feb 24 18:35:38 2017 Stefan RittPassing parameters to drsclThis is indeed currently not implemented.
But there is a simple C program drs_exam.cpp,
which connects to a board and safes some
  
  588   Fri Feb 24 17:34:28 2017 Tarik ZenginPassing parameters to drsclHi everyone,

I wonder if there is a way to pass
parameters to drscl. What I specifically
  
  587   Tue Jan 31 08:40:04 2017 Stefan RittLLD and ULD discriminations,Not inside the board. Each channel has
a single discriminator. You can select to
trigger on a rising or falling edge, but
  
  586   Tue Jan 31 01:37:35 2017 VO HONG HAILLD and ULD discriminations,Dear Stefan,
 Is there any way to develop
LLD and ULD discrimination in DSR-4 evaluation
board?
 Best regards,
V.H.Hai
  
  585   Mon Jan 30 16:37:33 2017 Stefan RittAND trigger problems In the evaluation board we use an ADCMP601
comparator, which has a setup and hold time
of 4.6 ns. So a pulse which exceeds the threshold
  
  584   Sat Jan 28 14:11:58 2017 Danny PetschkeAND trigger problems  Dear Stefan,

I have 2 identical pulses as a
splittet signal with an amplitude of 300mV.
  
ELOG V3.1.5-3fb85fa6