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+    Fri Apr 9 20:29:45 2021, Sean Quinn, Spikes/noise sensitive to clock settings?     +    Fri Apr 9 21:38:59 2021, Stefan Ritt, Spikes/noise sensitive to clock settings?     +    Fri Jun 24 09:57:36 2022, LynseyShun, Spikes/noise sensitive to clock settings?     +    Fri Jul 29 17:23:43 2022, Stefan Ritt, Spikes/noise sensitive to clock settings?  +    Tue May 27 13:46:18 2014, Dominik Neise, Spikes in DRS4 data on custom baord.     +    Tue May 27 16:07:17 2014, Stefan Ritt, Spikes in DRS4 data on custom baord.  +    Wed Aug 28 13:07:51 2013, Andrey Kuznetsov, Some bug fixes and questions     +    Thu Sep 5 10:01:00 2013, Andrey Kuznetsov, Some bug fixes and questions     +    Mon Sep 9 06:49:36 2013, Andrey Kuznetsov, Some bug fixes and questions     +    Wed Jan 15 16:15:00 2014, Stefan Ritt, Some bug fixes and questions     +    Wed Jan 15 17:02:58 2014, Stefan Ritt, Some bug fixes and questions     +    Wed Jan 15 17:11:14 2014, Stefan Ritt, Some bug fixes and questions  +    Wed Mar 5 21:54:13 2014, Hermann-Josef Mathes, Software drs-5.0.0 fails to compile (drsosc)     +    Thu Mar 6 11:12:44 2014, Stefan Ritt, Software drs-5.0.0 fails to compile (drsosc)    Wed Feb 16 14:06:45 2022, Dmitry Hits, Sliders missing in drsosc  +    Thu Feb 22 01:21:11 2024, Rod McInnis, Simulation of FPGA     +    Thu Feb 22 10:37:03 2024, Stefan Ritt, Simulation of FPGA  +    Tue Apr 28 11:44:07 2009, Stefan Ritt, Simple example application to read a DRS evaluation board     +    Wed Apr 29 07:57:33 2009, Stefan Ritt, Simple example application to read a DRS evaluation board     +    Mon Apr 5 17:57:41 2010, Heejong Kim, Simple example application to read a DRS evaluation board

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