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ID Date Author Subject
  770   Tue Aug 20 16:05:21 2019 Bill Ashmanskasshould one deassert DENABLE while writing the write-shift register?

Aha -- many thanks.  I think what tripped up my test logic is that the "done" state in drs4_eval5_app.vhd that executes post-readout sets DWRITE back to 1 (drs_write_set).  If one then writes to FPGA register 5 while the FSM is in the "idle" state, the conf_strobe and wsr_strobe states occur with DWRITE and DENABLE both asserted.  This is if one sets the "dactive" bit in the FPGA app code, which is probably not the usual use case.  Maybe using the real DRS.cpp avoids this situation.  (I was simulating your FPGA code to test my understanding of what our FPGA code should do.)

Anyway, our own use case is fine: as you suggest, we leave DENABLE asserted, but we deassert DWRITE while reading out or while changing DRS4 register values.

Thanks again,

Bill

 

 

Stefan Ritt wrote:

Hi Bill,

you keep DENABLE active all the time to keep the Domino Wave running, but you deassert DWRITE if you change any register via SRCLK. There is no shadow register, just a simple shift register, but with DWRITE being low, the domino circuitry does not touch it.

Best,
Stefan

Bill Ashmanskas wrote:

Hi Stefan,

We have for some time now been using custom firmware on a custom board to read waveforms out of DRS4 chips.  Now we are working on cascaded readout mode, 4 channels @ 2048 samples, WSREG=0x55, in order to allow for longer trigger latency.

Doing a testbench simulation of the FPGA code raised a question for me:  Do I need to deassert DENABLE while I shift a new 8-bit value into the write-shift register?  What happens if, during the few-hundred nanoseconds it takes to shift 8 bits into the register, the domino wave crosses cell 768, thereby shifting the write-shift register left by one bit?  Is this shifting suppressed when A=0b1101?  Or does the update of the actual write-shift register occur only once, after the 8th SRCLK cycle?  (Maybe one is really shifting bits into a shadow register that is copied all at once into the actual register?)

I notice in simulating your drs4_eval5_app.vhd that if one sets bit 27 ("drs_ctl_dactive") of register 0 (do not deassert DENABLE on trigger), then starts the domino wave (set bit 0 of register 0), then issues a software trigger, then later writes to register 5 (config register, wsreg, etc.), DENABLE is not in fact deasserted during the time when A=0b1100 (conf_setup, conf_strobe) or when A=0b1101 (wsr_setup, wsr_strobe).

But my simulation testbench includes a simplified Verilog model of my interpretation of the DRS4 data sheet, and my simulated DRS4 happened to cause the write-shift register to shift (256 samples before DTAP toggled) during your "wsr_strobe" FSM state, thus corrupting the value that was being shifted into the WSREG via SRIN and SRCLK.

So I'm curious:  to be safe, should one deassert DENABLE before updating the write-shift register, or is it safe to update it even while the domino wave is active and looping?  It seems easy enough to be safe, since we should only need to write to the WSREG once during the setup phase and then let it loop forever.

Many thanks,

Bill

 

  769   Tue Aug 20 10:44:45 2019 Stefan Rittshould one deassert DENABLE while writing the write-shift register?

Hi Bill,

you keep DENABLE active all the time to keep the Domino Wave running, but you deassert DWRITE if you change any register via SRCLK. There is no shadow register, just a simple shift register, but with DWRITE being low, the domino circuitry does not touch it.

Best,
Stefan

Bill Ashmanskas wrote:

Hi Stefan,

We have for some time now been using custom firmware on a custom board to read waveforms out of DRS4 chips.  Now we are working on cascaded readout mode, 4 channels @ 2048 samples, WSREG=0x55, in order to allow for longer trigger latency.

Doing a testbench simulation of the FPGA code raised a question for me:  Do I need to deassert DENABLE while I shift a new 8-bit value into the write-shift register?  What happens if, during the few-hundred nanoseconds it takes to shift 8 bits into the register, the domino wave crosses cell 768, thereby shifting the write-shift register left by one bit?  Is this shifting suppressed when A=0b1101?  Or does the update of the actual write-shift register occur only once, after the 8th SRCLK cycle?  (Maybe one is really shifting bits into a shadow register that is copied all at once into the actual register?)

I notice in simulating your drs4_eval5_app.vhd that if one sets bit 27 ("drs_ctl_dactive") of register 0 (do not deassert DENABLE on trigger), then starts the domino wave (set bit 0 of register 0), then issues a software trigger, then later writes to register 5 (config register, wsreg, etc.), DENABLE is not in fact deasserted during the time when A=0b1100 (conf_setup, conf_strobe) or when A=0b1101 (wsr_setup, wsr_strobe).

But my simulation testbench includes a simplified Verilog model of my interpretation of the DRS4 data sheet, and my simulated DRS4 happened to cause the write-shift register to shift (256 samples before DTAP toggled) during your "wsr_strobe" FSM state, thus corrupting the value that was being shifted into the WSREG via SRIN and SRCLK.

So I'm curious:  to be safe, should one deassert DENABLE before updating the write-shift register, or is it safe to update it even while the domino wave is active and looping?  It seems easy enough to be safe, since we should only need to write to the WSREG once during the setup phase and then let it loop forever.

Many thanks,

Bill

  768   Mon Aug 19 23:01:22 2019 Bill Ashmanskasshould one deassert DENABLE while writing the write-shift register?

Hi Stefan,

We have for some time now been using custom firmware on a custom board to read waveforms out of DRS4 chips.  Now we are working on cascaded readout mode, 4 channels @ 2048 samples, WSREG=0x55, in order to allow for longer trigger latency.

Doing a testbench simulation of the FPGA code raised a question for me:  Do I need to deassert DENABLE while I shift a new 8-bit value into the write-shift register?  What happens if, during the few-hundred nanoseconds it takes to shift 8 bits into the register, the domino wave crosses cell 768, thereby shifting the write-shift register left by one bit?  Is this shifting suppressed when A=0b1101?  Or does the update of the actual write-shift register occur only once, after the 8th SRCLK cycle?  (Maybe one is really shifting bits into a shadow register that is copied all at once into the actual register?)

I notice in simulating your drs4_eval5_app.vhd that if one sets bit 27 ("drs_ctl_dactive") of register 0 (do not deassert DENABLE on trigger), then starts the domino wave (set bit 0 of register 0), then issues a software trigger, then later writes to register 5 (config register, wsreg, etc.), DENABLE is not in fact deasserted during the time when A=0b1100 (conf_setup, conf_strobe) or when A=0b1101 (wsr_setup, wsr_strobe).

But my simulation testbench includes a simplified Verilog model of my interpretation of the DRS4 data sheet, and my simulated DRS4 happened to cause the write-shift register to shift (256 samples before DTAP toggled) during your "wsr_strobe" FSM state, thus corrupting the value that was being shifted into the WSREG via SRIN and SRCLK.

So I'm curious:  to be safe, should one deassert DENABLE before updating the write-shift register, or is it safe to update it even while the domino wave is active and looping?  It seems easy enough to be safe, since we should only need to write to the WSREG once during the setup phase and then let it loop forever.

Many thanks,

Bill

 

 

  767   Sat Jul 20 12:28:14 2019 Stefan RittTrace Impedance

The DRS4 input is high impedance. So if you like you can terminate it with 100 Ohm differentially and route it with 100 Ohm. But if you keep the lines short, the reflection is negligible. That’s what we made on the evaluation board.

Ismael Garcia wrote:

When you're refering to laying a 50 Ohm trace, you're referring to the SMA input and not the interface between the output of the Op-AMP(THS4508) buffer 
and the inputs  of the DRS4(IN0-IN8). Is there a recommended diffential impedance for IN0-IN8? 

Ismael

Stefan Ritt wrote:

The requiremnet is the same as for any high speed analog board, there is othing special with the DRS4. If you want to terminate your line with 50 Ohms and you want a matched impedance layout, you route all lines with 50 Ohms impedance. Truth is however that nothing is perfect. The SMA connector is not exactly 50 Ohm, the PCB gets a 10-20% variation depending on the manufacturer. So even if you try hard, you will never have a 50 Ohm matched impedance. On the evaluation board we made some compromises as you have seen, but for us the board works satisfactory even with this compromises, and you can test it yourself with real hardware (namely the evaluation board). If you can do a better job, try it. But usually these compromises have only little influence on the signal quality.

Stefan

Ismael Garcia wrote:

Hi Steffan,

              I'm an engineer at UCLA developing a board with the DRS4 chip. Our team has a question on what might be the required trace impedence for the analog inputs. Can that information be provided? 

Best Regards,
Ismael Garcia

 

 

 

  766   Fri Jul 19 01:37:09 2019 Ismael GarciaTrace Impedance

When you're refering to laying a 50 Ohm trace, you're referring to the SMA input and not the interface between the output of the Op-AMP(THS4508) buffer 
and the inputs  of the DRS4(IN0-IN8). Is there a recommended diffential impedance for IN0-IN8? 

Ismael

Stefan Ritt wrote:

The requiremnet is the same as for any high speed analog board, there is othing special with the DRS4. If you want to terminate your line with 50 Ohms and you want a matched impedance layout, you route all lines with 50 Ohms impedance. Truth is however that nothing is perfect. The SMA connector is not exactly 50 Ohm, the PCB gets a 10-20% variation depending on the manufacturer. So even if you try hard, you will never have a 50 Ohm matched impedance. On the evaluation board we made some compromises as you have seen, but for us the board works satisfactory even with this compromises, and you can test it yourself with real hardware (namely the evaluation board). If you can do a better job, try it. But usually these compromises have only little influence on the signal quality.

Stefan

Ismael Garcia wrote:

Hi Steffan,

              I'm an engineer at UCLA developing a board with the DRS4 chip. Our team has a question on what might be the required trace impedence for the analog inputs. Can that information be provided? 

Best Regards,
Ismael Garcia

 

 

  765   Thu Jul 18 11:37:56 2019 Stefan RittTrace Impedance

The requiremnet is the same as for any high speed analog board, there is othing special with the DRS4. If you want to terminate your line with 50 Ohms and you want a matched impedance layout, you route all lines with 50 Ohms impedance. Truth is however that nothing is perfect. The SMA connector is not exactly 50 Ohm, the PCB gets a 10-20% variation depending on the manufacturer. So even if you try hard, you will never have a 50 Ohm matched impedance. On the evaluation board we made some compromises as you have seen, but for us the board works satisfactory even with this compromises, and you can test it yourself with real hardware (namely the evaluation board). If you can do a better job, try it. But usually these compromises have only little influence on the signal quality.

Stefan

Ismael Garcia wrote:

Hi Steffan,

              I'm an engineer at UCLA developing a board with the DRS4 chip. Our team has a question on what might be the required trace impedence for the analog inputs. Can that information be provided? 

Best Regards,
Ismael Garcia

 

  764   Thu Jul 18 01:03:44 2019 Ismael GarciaTrace Impedance

Hi Steffan,

              I'm an engineer at UCLA developing a board with the DRS4 chip. Our team has a question on what might be the required trace impedence for the analog inputs. Can that information be provided? 

Best Regards,
Ismael Garcia

Attachment 1: DRS4_Analog_IN.PNG
DRS4_Analog_IN.PNG
  763   Mon Jul 15 19:34:25 2019 Brendan PosehnEvaluation Board Test Functionality

Hello Stefan, 

Thanks for the quick reply. The issue was a faulty SMA connector, should have checked this first. Signal looks good now.

Thanks for your time, 

Brendan

Stefan Ritt wrote:

Have you set the trigger correctly to the channel with your signal, polarity and level? Do you undersand the difference between normal and auto trigger? Why don't you post a screendump. Are you ABSOLUTELY SURE that you have a signal on your cable? Have you tried with another oscilloscope? Are you sure that your SMA connector is good?

Stefan

 

Brendan Posehn wrote:

Hello, 

I have recently obtained a DRS4 Evaluation Board (V5), but I am unable to register signals when using the DRS Oscilloscope application. There seems to be some difference in noise when I have an input connected to a signal or not, but I am unable to view a simple, 0.2V amplitude square wave or other small signals. The only way I have been able to view a waveform is when connecting the reference clock to all channels. When running 'info' in the DRS Command Line Interface I am shown correct information. I was wondering if there is any way for me to test the functionality of the board (specifially ability to read signals on Ch 1-4) to ensure that it is indeed working as expected? 

Thanks, 

Brendan

 

 

  762   Mon Jul 15 17:26:50 2019 Stefan RittEvaluation Board Test Functionality

Have you set the trigger correctly to the channel with your signal, polarity and level? Do you undersand the difference between normal and auto trigger? Why don't you post a screendump. Are you ABSOLUTELY SURE that you have a signal on your cable? Have you tried with another oscilloscope? Are you sure that your SMA connector is good?

Stefan

 

Brendan Posehn wrote:

Hello, 

I have recently obtained a DRS4 Evaluation Board (V5), but I am unable to register signals when using the DRS Oscilloscope application. There seems to be some difference in noise when I have an input connected to a signal or not, but I am unable to view a simple, 0.2V amplitude square wave or other small signals. The only way I have been able to view a waveform is when connecting the reference clock to all channels. When running 'info' in the DRS Command Line Interface I am shown correct information. I was wondering if there is any way for me to test the functionality of the board (specifially ability to read signals on Ch 1-4) to ensure that it is indeed working as expected? 

Thanks, 

Brendan

 

  761   Sat Jul 13 01:00:15 2019 Brendan PosehnEvaluation Board Test Functionality

Hello, 

I have recently obtained a DRS4 Evaluation Board (V5), but I am unable to register signals when using the DRS Oscilloscope application. There seems to be some difference in noise when I have an input connected to a signal or not, but I am unable to view a simple, 0.2V amplitude square wave or other small signals. The only way I have been able to view a waveform is when connecting the reference clock to all channels. When running 'info' in the DRS Command Line Interface I am shown correct information. I was wondering if there is any way for me to test the functionality of the board (specifially ability to read signals on Ch 1-4) to ensure that it is indeed working as expected? 

Thanks, 

Brendan

  760   Mon Jul 8 14:29:12 2019 Stefan Rittdrs_exam is always reading out a sin wave

Actually in the original drs_exam.cpp the sine wave oscillator is turned off with this command

/* use following line to turn on the internal 100 MHz clock connected to all channels  */
//b->EnableTcal(1);

If you remove the "//" then the generator gets enabled. Probably you did this by accident. With this line commented out, you see the proper input like this:

Event #0 ----------------------
  t1[ns]  u1[mV]  t2[ns] u2[mV]
  0.000     1.9   0.000    -2.4
  0.195     0.5   0.195     0.3
  0.391     0.1   0.391    -1.4
  0.586    -0.7   0.586    -0.4
  0.781    -1.1   0.781    -2.4
  0.977    -0.6   0.977     0.0
  1.172    -1.5   1.172    -2.8
  1.367    -0.4   1.367    -0.6
  1.562    -1.2   1.562    -3.8
  1.758    -1.5   1.758    -1.7
  1.953    -1.0   1.953    -3.3
  2.148    -0.7   2.148    -1.8
  2.344    -1.6   2.344    -4.2
  2.539     0.5   2.539    -1.5
  2.734     0.2   2.734    -3.6
...

167.969    -3.4 167.969    -5.2
168.164    -3.7 168.164    -3.6
168.359     0.0 168.359    -2.0
168.555     1.9 168.555    -0.2
168.750     2.8 168.750    -2.8
168.945     5.4 168.945    -1.4
169.141    18.0 169.141     1.2
169.336    26.6 169.336     2.7
169.531    46.2 169.531     0.4
169.727    56.2 169.727     1.6
169.922    93.3 169.922     0.1
170.117   115.6 170.117     0.0
170.312   174.4 170.312    -1.5
170.508   206.9 170.508    -0.8
170.703   282.2 170.703    -2.4
170.898   328.4 170.898    -1.2
171.094   419.6 171.094    -3.2
171.289   465.8 171.289    -2.5
171.484   500.0 171.484    -2.0
171.680   500.0 171.680    -0.6
171.875   500.0 171.875    -4.0
172.070   500.0 172.070    -1.1
172.266   500.0 172.266    -3.7
172.461   500.0 172.461    -2.1
172.656   500.0 172.656    -5.0
172.852   500.0 172.852    -3.3
173.047   500.0 173.047    -4.8
173.242   500.0 173.242    -4.1
173.438   500.0 173.438    -5.1
173.633   500.0 173.633    -3.3
173.828   500.0 173.828    -6.4
174.023   500.0 174.023    -3.9
174.219   500.0 174.219    -5.5
174.414   500.0 174.414    -3.2
174.609   500.0 174.609    -3.6
174.805   500.0 174.805    -2.6
175.000   500.0 175.000    -5.2
175.195   500.0 175.195    -2.7
175.391   434.3 175.391    -3.9
175.586   391.7 175.586    -2.4
175.781   312.2 175.781    -4.1
175.977   275.7 175.977    -1.8
176.172   202.4 176.172    -3.8
176.367   167.6 176.367    -1.4
176.562   117.4 176.562    -2.9
176.758    96.1 176.758    -2.3
176.953    62.8 176.953    -3.3
177.148    49.1 177.148    -1.8
177.344    35.9 177.344    -4.3
177.539    33.4 177.539    -2.6
177.734    30.4 177.734    -4.2
...

 

Si Xie wrote:

I see. Where is the code that we can use to turn off the generator? I thought the example is taking data with CH1 as the trigger.

For our board, which is BoardType == 9, it is running these lines:

      b->EnableTrigger(1, 0);           // enable hardware trigger
      b->SetTriggerSource(1<<0);        // set CH1 as source

Is that not using the hardware trigger with CH1 as the source?

 

Stefan Ritt wrote:

Sure, that’s correct. The example program turns on the internal sine wave generator in case people don’t have a real signal. That’s why it’s called „example“. Find the code which turns on the generator and change it. You will also have to change the trigger settings depending on your actual signal.

Stefan

 

Si Xie wrote:

We are using the drs_exam.cpp to read out waveforms, but it seems to be outputting only sin waves on all channels - as if it was reading out the simulated waveform from the oscilloscope program if we run it without the board plugged in. Does anyone know what is causing this?

We are taking data with a pulser plugged into channel 1, which produces a single pulse with width of 8ns, and nothing plugged into channel 2. 

Our board is as follows:

Found DRS4 evaluation board, serial #2567, firmware revision 21305
Board type: 9

The output is something like the following:

Event #0 ----------------------
  t1[ns]  u1[mV]  t2[ns] u2[mV]
  0.000  -452.7   0.026  -469.3
  0.289  -460.8   0.293  -469.8
  0.413  -477.3   0.400  -481.5
  0.642  -485.3   0.650  -482.4
  0.806  -486.9   0.821  -477.8
  1.086  -476.8   1.085  -457.2
  1.183  -467.3   1.162  -446.4
  1.450  -435.6   1.459  -405.1
  1.619  -410.1   1.630  -373.3
  1.843  -366.2   1.851  -323.9
  1.945  -342.9   1.948  -298.9
  2.221  -275.7   2.210  -229.3
  2.359  -237.6   2.357  -187.6
  2.602  -165.6   2.609  -111.2
  2.687  -141.1   2.697   -84.3
  2.976   -50.5   2.987     5.5
  3.164     8.4   3.144    53.3
  3.377    73.9   3.384   124.2
  3.503   111.4   3.506   158.0
  3.753   182.0   3.769   226.9
  3.924   227.5   3.929   265.8
 

 

 

 

  759   Wed Jun 26 15:17:51 2019 Si XieRunning drs_example.cpp

Hi Rodrigo, I'm wondering how you solved your original triggering problem. We are also having trouble with collecting data continously using the example. Thanks.

Rodrigo Trindade de Menezes wrote:

We found a way to solve the previous problem, but right now when we try to set the input range only -0.5 to 0.5 is working. When we set the function "SetInputRange(0.5)" for 0 to 1V the output is all zeros and with  "SetInputRange(0.45)" we just get all the outputs -49.9mV. What does that means? How to fix?

odrigo Trindade de Menezes wrote:

Hello,

We have been using the DRS4 evaluation board (S/N 2636) that works with the scope application. However we are trying to run the DRS4 evaluation board remotely by modifying the drs_exam.cpp to acquire and store data continuously.

We compiled the DRS_example.cpp without the wxWidgets but when we try to run the program, it appears to trigger on nonsense.  The program appears to not be sensitive to the trigger threshold (although for very large trigger threshold it gets stuck in a waiting mode).  Is there a way to ensure that the "normal" trigger mode is set?  We are worried that the auto mode is running.  Otherwise, not sure why the program is triggering on nonsense.  By the way, it does not work with the wxWidgets compiled either so we are worried that there is an additional flag that needs to be set. The routine does not appear to conduct a calibration -- is this not necessary?

Another issue that we are having is with the data set stored on the .txt file looks incorrect.  The time channel stops at 200 (but we think it should go up to 1024). In addition, the voltage channel appears to hover around small values near zero (as if triggering on noise).  The output file appears this way even when we change the threshold to much higher values.  It suggests that the trigger threshold is not actually being set? There are events where the output voltage appears to oscillate through huge negative and positive values too.  So not sure what's going on. 

Thanks!

Rodrigo

 

 

  758   Wed Jun 26 15:10:09 2019 Si Xiedrs_exam is always reading out a sin wave

I see. Where is the code that we can use to turn off the generator? I thought the example is taking data with CH1 as the trigger.

For our board, which is BoardType == 9, it is running these lines:

      b->EnableTrigger(1, 0);           // enable hardware trigger
      b->SetTriggerSource(1<<0);        // set CH1 as source

Is that not using the hardware trigger with CH1 as the source?

 

Stefan Ritt wrote:

Sure, that’s correct. The example program turns on the internal sine wave generator in case people don’t have a real signal. That’s why it’s called „example“. Find the code which turns on the generator and change it. You will also have to change the trigger settings depending on your actual signal.

Stefan

 

Si Xie wrote:

We are using the drs_exam.cpp to read out waveforms, but it seems to be outputting only sin waves on all channels - as if it was reading out the simulated waveform from the oscilloscope program if we run it without the board plugged in. Does anyone know what is causing this?

We are taking data with a pulser plugged into channel 1, which produces a single pulse with width of 8ns, and nothing plugged into channel 2. 

Our board is as follows:

Found DRS4 evaluation board, serial #2567, firmware revision 21305
Board type: 9

The output is something like the following:

Event #0 ----------------------
  t1[ns]  u1[mV]  t2[ns] u2[mV]
  0.000  -452.7   0.026  -469.3
  0.289  -460.8   0.293  -469.8
  0.413  -477.3   0.400  -481.5
  0.642  -485.3   0.650  -482.4
  0.806  -486.9   0.821  -477.8
  1.086  -476.8   1.085  -457.2
  1.183  -467.3   1.162  -446.4
  1.450  -435.6   1.459  -405.1
  1.619  -410.1   1.630  -373.3
  1.843  -366.2   1.851  -323.9
  1.945  -342.9   1.948  -298.9
  2.221  -275.7   2.210  -229.3
  2.359  -237.6   2.357  -187.6
  2.602  -165.6   2.609  -111.2
  2.687  -141.1   2.697   -84.3
  2.976   -50.5   2.987     5.5
  3.164     8.4   3.144    53.3
  3.377    73.9   3.384   124.2
  3.503   111.4   3.506   158.0
  3.753   182.0   3.769   226.9
  3.924   227.5   3.929   265.8
 

 

 

  757   Wed Jun 26 13:08:42 2019 Stefan Rittdrs_exam is always reading out a sin wave

Sure, that’s correct. The example program turns on the internal sine wave generator in case people don’t have a real signal. That’s why it’s called „example“. Find the code which turns on the generator and change it. You will also have to change the trigger settings depending on your actual signal.

Stefan

 

Si Xie wrote:

We are using the drs_exam.cpp to read out waveforms, but it seems to be outputting only sin waves on all channels - as if it was reading out the simulated waveform from the oscilloscope program if we run it without the board plugged in. Does anyone know what is causing this?

We are taking data with a pulser plugged into channel 1, which produces a single pulse with width of 8ns, and nothing plugged into channel 2. 

Our board is as follows:

Found DRS4 evaluation board, serial #2567, firmware revision 21305
Board type: 9

The output is something like the following:

Event #0 ----------------------
  t1[ns]  u1[mV]  t2[ns] u2[mV]
  0.000  -452.7   0.026  -469.3
  0.289  -460.8   0.293  -469.8
  0.413  -477.3   0.400  -481.5
  0.642  -485.3   0.650  -482.4
  0.806  -486.9   0.821  -477.8
  1.086  -476.8   1.085  -457.2
  1.183  -467.3   1.162  -446.4
  1.450  -435.6   1.459  -405.1
  1.619  -410.1   1.630  -373.3
  1.843  -366.2   1.851  -323.9
  1.945  -342.9   1.948  -298.9
  2.221  -275.7   2.210  -229.3
  2.359  -237.6   2.357  -187.6
  2.602  -165.6   2.609  -111.2
  2.687  -141.1   2.697   -84.3
  2.976   -50.5   2.987     5.5
  3.164     8.4   3.144    53.3
  3.377    73.9   3.384   124.2
  3.503   111.4   3.506   158.0
  3.753   182.0   3.769   226.9
  3.924   227.5   3.929   265.8
 

 

  756   Tue Jun 25 23:04:29 2019 Si Xiedrs_exam is always reading out a sin wave

We are using the drs_exam.cpp to read out waveforms, but it seems to be outputting only sin waves on all channels - as if it was reading out the simulated waveform from the oscilloscope program if we run it without the board plugged in. Does anyone know what is causing this?

We are taking data with a pulser plugged into channel 1, which produces a single pulse with width of 8ns, and nothing plugged into channel 2. 

Our board is as follows:

Found DRS4 evaluation board, serial #2567, firmware revision 21305
Board type: 9

The output is something like the following:

Event #0 ----------------------
  t1[ns]  u1[mV]  t2[ns] u2[mV]
  0.000  -452.7   0.026  -469.3
  0.289  -460.8   0.293  -469.8
  0.413  -477.3   0.400  -481.5
  0.642  -485.3   0.650  -482.4
  0.806  -486.9   0.821  -477.8
  1.086  -476.8   1.085  -457.2
  1.183  -467.3   1.162  -446.4
  1.450  -435.6   1.459  -405.1
  1.619  -410.1   1.630  -373.3
  1.843  -366.2   1.851  -323.9
  1.945  -342.9   1.948  -298.9
  2.221  -275.7   2.210  -229.3
  2.359  -237.6   2.357  -187.6
  2.602  -165.6   2.609  -111.2
  2.687  -141.1   2.697   -84.3
  2.976   -50.5   2.987     5.5
  3.164     8.4   3.144    53.3
  3.377    73.9   3.384   124.2
  3.503   111.4   3.506   158.0
  3.753   182.0   3.769   226.9
  3.924   227.5   3.929   265.8
 

  755   Mon Jun 24 23:07:35 2019 Andrew PeckEvaluation firmware wait_vdd state

Dear Stefan, 

Thanks so much for clarifying this. We made wait_vdd a parameter controlled by software and will try to experiment with it to find some compromise between deadtime and the offset added by the droop in VDD. 

Best regards, 

Andrew

Stefan Ritt wrote:

Dear Andrew,

the posting you mention is still accurate. Any power supply will drop when you start the Domino wave, no matter how big your capacitor is. Unfortunately the output signal of the DRS4 scales with VDD. So if your VDD drops by 40 mV and you get a trigger and you immediately start the readout, the output baseline will also be shifted by about 40 mV. If you are sensitive to dead time, you can remove the wait_vdd state completely, but then you have to deal with varying baseline shifts. If you have narrow signals sitting on a broad baseline, you can correct for this by measuring the baseline outside your signal, then subtracting it before integrating your pulse. If you have lots of pile-up in your signals, it might sometimes be hard to evaluate the baseline on an event-by-event basis.

Stefan

Andrew Peck wrote:

Dear Stefan,

I am working with others at UCLA on a custom made board built around the DRS4. We are in the process of writing firmware so I am adapting the readout state machine from the evaluation board firmware.

I see in the state machine of the eval board firmware that after a trigger is received, the FPGA goes into the start readout state and then into "wait_vdd", where the FPGA waits "~120 us for vdd to stabilize" before reading out the ADC.

Our application is sensitive to deadtime and this wait_vdd state adds very significantly.  I am trying to find anything explaining the necessity of wait_vdd in the documentation / elog and have only found so far your old forum posting, https://elog.psi.ch/elogs/DRS4+Forum/12

Does this forum posting explain wait_vdd or is there a another purpose that I have missed?

If this post is relevant to wait_vdd, does the advice of large capacitance and an LDO with fast transient response still apply or are there any new recommendations?

Thank you,

Andrew Peck

 

 

  754   Fri Jun 21 12:54:47 2019 Stefan RittEvaluation firmware wait_vdd state

Dear Andrew,

the posting you mention is still accurate. Any power supply will drop when you start the Domino wave, no matter how big your capacitor is. Unfortunately the output signal of the DRS4 scales with VDD. So if your VDD drops by 40 mV and you get a trigger and you immediately start the readout, the output baseline will also be shifted by about 40 mV. If you are sensitive to dead time, you can remove the wait_vdd state completely, but then you have to deal with varying baseline shifts. If you have narrow signals sitting on a broad baseline, you can correct for this by measuring the baseline outside your signal, then subtracting it before integrating your pulse. If you have lots of pile-up in your signals, it might sometimes be hard to evaluate the baseline on an event-by-event basis.

Stefan

Andrew Peck wrote:

Dear Stefan,

I am working with others at UCLA on a custom made board built around the DRS4. We are in the process of writing firmware so I am adapting the readout state machine from the evaluation board firmware.

I see in the state machine of the eval board firmware that after a trigger is received, the FPGA goes into the start readout state and then into "wait_vdd", where the FPGA waits "~120 us for vdd to stabilize" before reading out the ADC.

Our application is sensitive to deadtime and this wait_vdd state adds very significantly.  I am trying to find anything explaining the necessity of wait_vdd in the documentation / elog and have only found so far your old forum posting, https://elog.psi.ch/elogs/DRS4+Forum/12

Does this forum posting explain wait_vdd or is there a another purpose that I have missed?

If this post is relevant to wait_vdd, does the advice of large capacitance and an LDO with fast transient response still apply or are there any new recommendations?

Thank you,

Andrew Peck

 

  753   Thu Jun 20 01:36:48 2019 Andrew PeckEvaluation firmware wait_vdd state

Dear Stefan,

I am working with others at UCLA on a custom made board built around the DRS4. We are in the process of writing firmware so I am adapting the readout state machine from the evaluation board firmware.

I see in the state machine of the eval board firmware that after a trigger is received, the FPGA goes into the start readout state and then into "wait_vdd", where the FPGA waits "~120 us for vdd to stabilize" before reading out the ADC.

Our application is sensitive to deadtime and this wait_vdd state adds very significantly.  I am trying to find anything explaining the necessity of wait_vdd in the documentation / elog and have only found so far your old forum posting, https://elog.psi.ch/elogs/DRS4+Forum/12

Does this forum posting explain wait_vdd or is there a another purpose that I have missed?

If this post is relevant to wait_vdd, does the advice of large capacitance and an LDO with fast transient response still apply or are there any new recommendations?

Thank you,

Andrew Peck

  752   Fri Apr 12 12:50:18 2019 Stefan Rittmulti-board

If you have two signal going through two cables, the cable have never the same length (on a scale of picoseconds), and you have to calibrate that anyway. So a proper timing calibration is not a crutch.

What do you mean by "manual 50ps"? The manual does not mention any resolution. In my experience, you can achieve about 10ps between channels of the SAME board easily. The phase shift between boards in multi-mode is always there, unfortunately there are no cable which conduct current faster than the speed of light! What you can do is to split a common reference clock and send a copy to one channel of each board, then calculate the timing relative to the next edge in that reference signal. This way you get rid of the phase shift, but this is also a kind of calibration, so in your laguange that would be "a big crutch".

Stefan

 

Lev Pavlov wrote:

 

I understand this, thanks. But my Chief does not understand this, he wants to see the phase difference without “crutches”. And what is meant in the manual 50 ps resolution? Maybe I just do not understand something? And if you submit a reference signal not in the mode of a garland, but simultaneously in parallel to all the boards, will this shift go? Thanks

Lev Pavlov

Stefan Ritt wrote:

Subtract 16 ns from your measured value ;-)

Stefan

Lev Pavlov wrote:

Good afternoon, I use 5 boards in multi-mode, everything is connected according to the instructions. Can I measure the phase difference between the two signals on channel 1 and channel 20? with each board the phase shift is added +16 ns I can not figure out how to compensate for this. give thanks

 

 

 

  751   Fri Apr 12 09:59:15 2019 Lev Pavlovmulti-board

 

I understand this, thanks. But my Chief does not understand this, he wants to see the phase difference without “crutches”. And what is meant in the manual 50 ps resolution? Maybe I just do not understand something? And if you submit a reference signal not in the mode of a garland, but simultaneously in parallel to all the boards, will this shift go? Thanks

Lev Pavlov

Stefan Ritt wrote:

Subtract 16 ns from your measured value ;-)

Stefan

Lev Pavlov wrote:

Good afternoon, I use 5 boards in multi-mode, everything is connected according to the instructions. Can I measure the phase difference between the two signals on channel 1 and channel 20? with each board the phase shift is added +16 ns I can not figure out how to compensate for this. give thanks

 

 

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