Mon May 2 14:31:28 2016, Dmitry Hits, two DRS4 boards configuration with 2048 samples each
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Hi Stefan
Any chance you have time to fix the software for multiboard configuration with 2048 samples each. I tried 5.0.5, but drsosc still shows
only half of the waveform. |
Tue Mar 20 16:23:33 2012, Martin Petriska, triger for measuring time between pulses in channels
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I have two BaF2 detectors with PMT connected to Ch1 and Ch2. At this time Im using external triger module to start DRS4. My evalution board is
version 3 so I have no possibility to trigger on two or more pulses occurence on different channels. But I have this idea, trigger with analog trigger
on channel 1 (start detector) will start measurement on all channels. After that using FPGA inside EVM to look if some value in Ch2 is bigger as treshold |
Tue Mar 20 16:33:50 2012, Stefan Ritt, triger for measuring time between pulses in channels
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Martin Petriska wrote:
I have two BaF2 detectors with PMT connected to Ch1 and Ch2. At this time Im using external triger |
Wed Mar 21 09:33:00 2012, Martin Petriska, triger for measuring time between pulses in channels
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Stefan Ritt wrote:
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Wed Mar 21 09:39:33 2012, Stefan Ritt, triger for measuring time between pulses in channels
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Martin Petriska wrote:
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Wed Jun 20 10:40:21 2012, Ivan Petrov, triger for measuring time between pulses in channels
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Stefan Ritt wrote:
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Wed Jun 20 12:45:05 2012, Stefan Ritt, triger for measuring time between pulses in channels
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Ivan Petrov wrote:
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Wed Jun 20 14:36:01 2012, Ivan Petrov, triger for measuring time between pulses in channels
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Stefan Ritt wrote:
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Wed Jun 20 14:44:38 2012, Stefan Ritt, triger for measuring time between pulses in channels
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Ivan Petrov wrote:
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Sat Jun 23 00:29:52 2012, Andrey Kuznetsov, triger for measuring time between pulses in channels
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Stefan Ritt wrote:
On the evaluation board, yes. This board is not optimized for high readout rate. If you do your own |
Mon Jun 25 14:21:13 2012, Stefan Ritt, triger for measuring time between pulses in channels
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Andrey Kuznetsov wrote:
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Wed May 13 09:31:18 2015, Chenfei Yang, transparent-mode voltage
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Hello Mr. Stefan Ritt
For DRS4 differential inputs ranges form 500mV to 1100mV, with ROFS set to 1.55V, O_OFS set to 1.3V, the outputs of DRS4 is shown in the
attachment. |
Wed May 13 09:45:51 2015, Stefan Ritt, transparent-mode voltage
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The ROFS signal has no effect in the transparent mode, so you have to adjust O_OFS between sampling and transparent mode accordingly. Either use a DAC
or two voltages with an analog switch.
Chenfei |
Wed May 13 09:55:09 2015, Chenfei Yang, transparent-mode voltage
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Here's the problem. My external ADC has 2Vpp differtial input voltage range. And the common-mode voltage of the inputs need to be 1.3V. I cannot
make both the transparent-output and the readout-output meet the ADC input requirement.
Stefan |
Wed May 13 10:16:40 2015, Stefan Ritt, transparent-mode voltage
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I see your point. Actually I will soon have the same issue since we design right now a board with an AD9637 using the transparent mode. Which one are
you using? The common mode range given in the datasheet is limited to guarantee optimal performance. But some ADCs allow a slightly bigger common mode
range with reduced performance, but which might still be ok for some application. A "real" solution would be to put switchable level shifters |
Wed May 13 10:27:43 2015, Chenfei Yang, transparent-mode voltage
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I'm using an AD9252, 0.9V common mode voltage is suggested and I already use 8 un-switchable level shifters. Just as you said, this common mode range
is recommended for optimum performance and the device can function over a wider range with reasonable performance. So I think I could
adjust O_OFS to a minor level during transparent output. |
Wed May 13 12:34:49 2015, Stefan Ritt, transparent-mode voltage
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There might be a solution. How do you bias th input of the DRS4 chip? If you use a scheme as described in elog:84,
you can bias DRS_IN+ and DRS_IN- as desired. Take for example a board input range of 0-1V. For a 0V input, you bias DRS_IN+ and DRS_IN- both
with 0.9V. A 1V input signal then puts DRS_IN+ to 1.4V and DRS_IN-to 0.4 V. In the transparent mode, DRS_OUT+ = DRS_IN+ and DRS_OUT- = O-OFS |
Wed May 13 12:52:22 2015, Chenfei Yang, transparent-mode voltage
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Yes. I use exactly the same scheme as you mentioned. I'll try your solution.
Stefan
Ritt wrote:
There might be a solution. How do you bias th input |
Wed May 13 16:13:07 2015, Chenfei Yang, transparent-mode voltage
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If using a ROFS of 0.9V, the input would not between 1.05V~2.05V better non-linearity area. Is that appropriate?
Stefan
Ritt wrote:
There might be a solution. How do you bias th input |
Wed May 13 16:25:24 2015, Stefan Ritt, transparent-mode voltage
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To get the good linearity, you need indeed ROFS = 1.05V. With a O-OFS of 0.9V, a zero input signal would give you DRS_OUT+=1.05V and DRS_OUT-=0.75V.
I think this is till in the range of your ADC, right? So it's a tradeoff between linearity and available range. I do not know how nonlinear the DRS4
will be for ROFS < 1.05V, you have to try. If it's getting too bad, you still can correct for this off-line. |