 Tue Jun 22 10:50:19 2010, Jinhong Wang, Reset of DRS4
|
Hi Stefan,
I found DRS draw a lot of current when applied Reset after power on, and the PLL does not work properly. I believe
there was something that I misunderstood. So, what will happen when Reset is applied more than once after power on? . Though the chip worked well |
 Tue Jun 22 11:29:26 2010, Jinhong Wang, Reset of DRS4
|
Stefan Ritt wrote:
|
|
Tue Jun 22 11:37:42 2010, Jinhong Wang, Reset of DRS4
|
Stefan Ritt wrote:
|
|
Mon Jul 19 12:07:04 2010, Jinhong Wang, Fixed Patter Timing Jitter
|
| Hi Stefan, can you give some suggestions on determination of fixed pattern timing jitter of DRS4? Thanks~ |
|
Wed Jul 21 10:46:32 2010, Jinhong Wang, ENOB of DRS
|
Hi, Stefan, I see in your ppt "Design and performance of 6 GSPS waveform digitizing chip DRS4" , you define DRS4 ENOB as 1Vpp/0.35mv(RMS)
= 11.5bit, where, 1Vpp is the linearity input range, and 0.35mv is the rms voltage after offset correction. What I understand is that 0.35mV is obtained
from DC offset Correction, hence 11.5 bit is for DC input, am i right? If true, what about ENOB for AC input in the whole analog bandwidth? thanks~ |
|
Tue Oct 12 03:53:37 2010, Jinhong Wang, Reference design for DRS4 active input buffer
|
Stefan Ritt wrote:
The design of high frequency differential input stages with the DRS4 is a challenge, since the chip |
Mon Jul 4 05:06:00 2011, Jinhong Wang, Fixed Patter Timing Jitter 
|
Stefan Ritt wrote:
|
|
Tue Jul 12 09:49:08 2011, Jinhong Wang, Fixed Patter Timing Jitter
|
Stefan Ritt wrote:
|
|
Thu Dec 27 00:12:12 2012, Jinhong Wang, variation of sampling capacitors
|
Hi Stefan,
A quick question, what is the typical variation of the sampling capacitors in DRS4? Will this variation be significant to affect your sampling
result? |
|
Thu Dec 27 18:15:14 2012, Jinhong Wang, variation of sampling capacitors
|
Stefan Ritt wrote:
|
|
Fri Feb 1 17:43:48 2013, Jinhong Wang, variation of sampling capacitors
|
Jinhong Wang wrote:
|
|
Tue Jul 19 02:35:04 2022, Jingyu Zhang, Increase event rate, use ROI mode, and install sw from source in Mac
|
Dear experts,
We are trying to increase the event rate of the DRS4. We looked into the ROI
but couldn’t figure out how to run in ROI mode. We are wondering if there is pre-existing firmware for this? We also tried to download and build |
|
Tue Mar 28 21:53:12 2017, Jim Freeman, drscl doesn't find eval board but drsosc does (Windows 7)
|
I cannot find the EVAL board using drscl version 5.06 while the drsosc works fine. I tried 2 different eval boards and 2 different computers and the
same effect. I looked under device manager at the libusb and the drs4 was there, and checked the driver which was found to be up to date. |
|
Tue Mar 26 01:17:59 2013, Jill Russek, cascading -- DRS4 Osci.cpp & DRS.cpp
|
All I'm trying to do is cascade one input signal, though all available channels, so that I end up with 8*1024 bins per event.
Here is the read out on my board/chip: |
|
Fri Apr 5 02:21:33 2013, Jill Russek, cascading -- DRS4 Osci.cpp & DRS.cpp
|
Stefan Ritt wrote:
|
|
Wed Apr 10 22:41:21 2013, Jill Russek, cascading -- DRS4 Osci.cpp & DRS.cpp
|
Stefan Ritt wrote:
|
|
Thu Apr 11 23:32:57 2013, Jill Russek, cascading -- DRS4 Osci.cpp & DRS.cpp
|
Stefan Ritt wrote:
|
|
Mon Sep 6 14:42:23 2021, Jiaolong, how to acquire the stop channel with 2x4096 cascading
|
Hi Steffan,
I have a question about how to acquire the stop channel:
Process: Configure the Write Shift Register with 00010001b to achieve 4-channel cascading, then after a trigger, |
|
Fri Nov 5 01:10:25 2021, Jiaolong, how to acquire the stop channel with 2x4096 cascading
|
Jiaolong
wrote:
Hi Steffan, |
|
Fri Nov 5 01:12:10 2021, Jiaolong, how to acquire the stop channel with 2x4096 cascading
|
Thanks for your advice. The problem has been solved by setting the srin again while reading out from srout.
Stefan
Ritt wrote:
The problem must be on your side, since the Write Shift Register readout |