 Mon Feb 29 13:33:06 2016, Dmitry Hits, two DRS4 boards configuration with 2048 samples each
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Dear Stefan,
I daisy-chained two boards (master sn#: 2514 - slave sn#: 2513) each with 2048 samples. However, when I use drsosc and put check mark in "configure
multi-board daisy-chain" I see only 1024 samples. Namely, the first 1024 samples, the last part is missing. When I remove this check mark, I |
 Mon May 2 14:31:28 2016, Dmitry Hits, two DRS4 boards configuration with 2048 samples each
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Hi Stefan
Any chance you have time to fix the software for multiboard configuration with 2048 samples each. I tried 5.0.5, but drsosc still shows
only half of the waveform. |
Wed Feb 16 14:06:45 2022, Dmitry Hits, Sliders missing in drsosc 
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Hi everyone,
Did anyone have a "missing sliders problem" in GUI (see attachment) accompanied by the following message in the terminal.
(drsosc:4611): Gtk-WARNING **: 14:05:11.249: Negative content width -4 (allocation 20, extents 12x12) while allocating gadget (node scale, owner |
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Thu Nov 16 02:55:44 2017, Diego Yankelevich, Averaging capabilities
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The Display window in the Oscilloscope software shows averaging capabilites but I have not been able to activate these. Is it possible to activate averaging
with the existing oscilloscope software? Thanks |
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Tue Dec 12 00:25:50 2017, Diego Yankelevich, External trigger using Raspberry Pi
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Dear Steffan:
We have been able to use the DRS4 using a Raspberry Pi but we have not been able to use the external trigger. What we are doing is basically
comment out the code shown below (downloaded from PSI) to use the hardware trigger and uncomment the code to use the external trigger. We have not been |
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Thu Mar 14 03:43:49 2019, Deepak Samuel, How to buy DRS evaluation kit
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Dear Stefan,
I have emailed drs4@psi.ch a couple of times regarding the pricing of the evaluation kits for academic use in India and have not received any
reply and hence writing in this forum. Could you please help me in this? |
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Thu Nov 8 11:44:35 2018, Davide Depaoli, Timing Issue
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Hi,
We are using the DRS4 Evaluation Board as a digitizer in our laboratory.
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Thu Nov 8 12:02:34 2018, Davide Depaoli, Timing Issue
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Thanks a lot for the quick response.
We will do as you suggest.
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Mon Oct 14 09:32:33 2019, Danyang, how to acquire the stop position with channel cascading
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Hi Steffan,
In DSR4 DATASHEET Rev.0.9 Page13, there is a paragraph "If the DRS4 is configured for channel cascading
or daisy chaining, it is necessary to know which the current channel is where the sampling has been stopped. This can be |
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Mon Oct 14 11:45:06 2019, Danyang, how to acquire the stop position with channel cascading
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I tried the logic in my designed board. The results are shown in the picture: Srout keeps low when A3-A0 is
set to 1101 and srclk is set as you mentioned. And the drs4 chip does not output sine wave in such configuration.
Srout signal only reacts after the rsrload signal is pulled high and A3-A0 is not 1101. |
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Mon Oct 14 13:44:26 2019, Danyang, how to acquire the stop position with channel cascading
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Yes, firstly I configured the chip with 4x2048 bins by setting the Write Shift Register to 01010101b， A3-A0 keeps 1101----> secondly
I enabled the domino wave, wait some time for stable, A3-A0 keeps 1111 ---->thirdly stops the domino wave when the trigger comes,
A3-A0 keeps 1101 (or 1010, 0000)----> forthly send the clock pulse to the srclk pin, A3-A0 keeps 1101, srout |
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Tue Oct 15 08:14:17 2019, Danyang, how to acquire the stop position with channel cascading
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Thanks a lot. The problem is solved when A3-A0 is set 1101 and srclk keeps low.
Best Regards,
Danyang |
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Sun Oct 9 10:43:35 2016, Danny Petschke, time difference between 2 channels only ~30-35ps @ 5GSmples/s
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(Board Type:9, DRS4)
Hello,
I´m trying to reach the timig resolution of about 2.5ps as written in the manual. |
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Mon Oct 10 11:30:37 2016, Danny Petschke, time difference between 2 channels only ~30-35ps @ 5GSmples/s
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Hello Stefan,
Chn2 & Chn3 were used for delay-determination as you can see on the second picture.
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Tue Oct 11 09:04:33 2016, Danny Petschke, time difference between 2 channels only ~30-35ps @ 5GSmples/s
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Hello Stefan,
thanks for the paper. That makes sense. I thought about sth. like that but wasn`t sure. Couldn´t check higher frequencies (limit of my
function generator). |
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Sat Jan 28 14:11:58 2017, Danny Petschke, AND trigger problems
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Dear Stefan,
I have 2 identical pulses as a splittet signal with an amplitude of 300mV. Range is -0.5-0.5V, 5.12GSamp using the Evaluation-Board. Both signals
are triggered in AND logic. One of the signals is delayed by a fixed value of 1-50ns for testing. On increasing the trigger Level from 10% to 50% of amplitude |
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Thu Mar 19 07:37:52 2015, Daniel Stricker-Shaver, Running 2 instances of a DRS DAQ program
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I don't know if it helps, but we measured the time resolution between two independendly running v3 boards using a single PC (latest software) in
Linux. (http://arxiv.org/abs/1405.4975)
You start the DRS DAQ program with only one USB board connected, first. Afterwards connect the second board and start another session. If you |
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Tue Apr 21 13:03:38 2015, Daniel Stricker-Shaver, DRS4 Evaluation Board Baseline/Voltage Calibration
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I also use Ubuntu 14.04 LTS and for my V3 borad I have to use drsosc 4.x or ealier to perform the calibration.
Stefan
Ritt wrote:
1) I tried to cablirate a V5 board with drsosc 5.0.3 and it just worked |
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Sat Apr 23 12:33:17 2016, Daniel Stricker-Shaver, Negative fCellDT values from GetTimeCalibration()
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Hi Kyle,
If I remember right the negative sampling width happens only for 498 and at high sampling speeds. It is described in a paper from Stefan:
http://arxiv.org/pdf/1405.4975.pdf |
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Mon Mar 21 10:38:27 2016, Daniel Dribin, DRS Oscilloscope freezing after a long run
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Dear Stefan Ritt,
I am using a DRS4 v5 to do timing measurements of Positron lifetime. I use the DRS Oscilloscope with triggering on 2 channels when I have
a coincidence. Attached is a picture with all the setting that I use. When I use the DRS4 for a long measurements of 5 million events for a couple of hours, |