Wed May 5 10:12:44 2021, Stefan Ritt, recording only timestamp and amplitude and/or filesize maximum
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The maximum file size depends on the underlying linux file system. Common values are 4-16 GBytes.
Stefan
Abaz |
Tue Nov 26 15:36:39 2013, Dmitry Hits, reducing sampling speed
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Dear Stefan
Is there an easy way to reduce sampling speed below 0.7 GSPS? I would like to record traces up to 5 usec long.
Thank you |
Tue Nov 26 15:38:13 2013, Stefan Ritt, reducing sampling speed
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Dmitry Hits wrote:
Dear Stefan |
Wed Apr 27 08:14:14 2016, Toshihiro Nonaka, serial number problem
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Dear all,
I'm using 3 DRS boards simultaneously and their serial numbers are 2169, 2170, 2172 respectively.
Recently however, I obtain serial number "0" by DRSBoard::GetBoardSerialNumber() for #2172 board. |
Wed Apr 27 09:04:01 2016, Stefan Ritt, serial number problem
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If dis- and reconnecting the board does not help, there is the (small) chance that the serial number got erased in the board. You can re-set it with
the "drscl" command line tool:
$ drscl |
Wed Apr 27 09:51:37 2016, Toshihiro Nonaka, serial number problem
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The serial number has been fixed by using drscl. Thank you!
Stefan
Ritt wrote:
If dis- and reconnecting the board does not help, there is the (small) |
Mon Aug 19 23:01:22 2019, Bill Ashmanskas, should one deassert DENABLE while writing the write-shift register?
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Hi Stefan,
We have for some time now been using custom firmware on a custom board to read waveforms out of DRS4 chips. Now we are working on cascaded
readout mode, 4 channels @ 2048 samples, WSREG=0x55, in order to allow for longer trigger latency. |
Tue Aug 20 10:44:45 2019, Stefan Ritt, should one deassert DENABLE while writing the write-shift register?
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Hi Bill,
you keep DENABLE active all the time to keep the Domino Wave running, but you deassert DWRITE if you change any register via SRCLK. There is
no shadow register, just a simple shift register, but with DWRITE being low, the domino circuitry does not touch it. |
Tue Aug 20 16:05:21 2019, Bill Ashmanskas, should one deassert DENABLE while writing the write-shift register?
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Aha -- many thanks. I think what tripped up my test logic is that the "done" state in drs4_eval5_app.vhd that executes post-readout sets
DWRITE back to 1 (drs_write_set). If one then writes to FPGA register 5 while the FSM is in the "idle" state, the conf_strobe and wsr_strobe
states occur with DWRITE and DENABLE both asserted. This is if one sets the "dactive" bit in the FPGA app code, which is probably not the |
Fri May 16 14:04:47 2014, Benjamin LeGeyt, simultaneous writing and reading with region of interest mode?
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Hello!
We're developing electronics based on the DRS4 to read out a breast PET scanner and our event rate will be quite high so we're concerned about
dead-time. with that in mind, I have a question regarding the mode of simultaneous writing and reading that is described in the DRS4 data sheet. |
Mon May 19 08:04:57 2014, Stefan Ritt, simultaneous writing and reading with region of interest mode?
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Benjamin LeGeyt wrote:
Hello! |
Wed Mar 14 00:38:15 2018, Will Flanagan, sub-ms precision timestamps?
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Dear DRS4 community,
Is there a way to extract timestamps with sub-ms precision? The milliseconds of an event is clearly given when unpacking the header. I would
like to determine how far apart events are when they are within the same millisecond. |
Thu Mar 15 08:44:26 2018, Stefan Ritt, sub-ms precision timestamps?
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Putting sub-ms precision into the header does not make sense, since the USB transfer only happens in time-slots of about 2 ms. To get better timing,
you would need a hardware time clock in the FPGA, which does not exist right now.
Best, |
Mon Nov 18 15:49:01 2013, Dmitry Hits, synchronisation of readouts of two boards for offline analysis
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Dear Stefan,
I am trying to synchronise the readout of two test boards, one is the DRS4 test board, the other is PSI46 test board (used for the readout of CMS
pixel chip) for the offline analysis. I think that the most secure way to accomplish this is to pass a trigger number from one test board to the other. |
Mon Nov 18 16:00:26 2013, Stefan Ritt, synchronisation of readouts of two boards for offline analysis
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Dmitry Hits wrote:
Dear Stefan, |
Mon Dec 16 11:09:25 2013, Dmitry Hits, synchronisation of readouts of two boards for offline analysis
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Stefan Ritt wrote:
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Tue Dec 17 08:45:32 2013, Stefan Ritt, synchronisation of readouts of two boards for offline analysis
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Dmitry Hits wrote:
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Fri Sep 12 11:52:21 2014, Dmitry Hits, synchronizing two DRS4 evaluation boards readout with one computer
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Hi everyone,
Has anyone tried to synchronize 2 (two) DRS4 evaluation boards readout by the same computer? I have read about some attempts on this board in the
past, but I do not know if they have succeeded. If yes, could you share your experience and/or software. |
Fri Sep 12 13:00:04 2014, Stefan Ritt, synchronizing two DRS4 evaluation boards readout with one computer
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Dmitry Hits wrote:
Hi everyone, |
Fri Sep 12 13:37:42 2014, Dmitry Hits, synchronizing two DRS4 evaluation boards readout with one computer
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Stefan Ritt wrote:
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