 Wed Oct 15 10:14:32 2014, Simon Weingarten, Clock settings in daisy chain DAQ
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Hi,
I'm currently working on a little DAQ system with four DRS evaluation boards. Do i need to apply any specific settings when using the clock in/out
connectors for synchronization? I do not see anything like that in the drs_exam_multi example. |
 Wed Oct 15 10:52:58 2014, Stefan Ritt, Clock settings in daisy chain DAQ
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Simon Weingarten wrote:
Hi, |
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Wed Oct 15 11:34:43 2014, Simon Weingarten, Clock settings in daisy chain DAQ
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Stefan Ritt wrote:
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Wed Oct 15 12:15:58 2014, Stefan Ritt, Clock settings in daisy chain DAQ 
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Here is the full version of the program with clock daisy-chaining. Before switching to the external clock, it checks if the clock really
is there (by reading an internal scaler), and only then enables it. Note that the code also works without clock daisy-chaining. But without clock daisy-chaining
your have some 400 ps time resolution between boards, and with clock daisy-chaining you get some 60 ps. |
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Fri Apr 17 10:07:38 2015, Simon Weingarten, Clock settings in daisy chain DAQ
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Hi Stefan,
do you know how these numbers (400ps and 60ps) scale with the sampling rate? The manual says they are for 5GS/s, do they change with slower sampling?
Thanks and best regards, |
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Mon Apr 20 13:08:24 2015, Stefan Ritt, Clock settings in daisy chain DAQ
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The resolution coming from the sampling rate goes into these numbers, but just marginally. At 5 GSPS, you get a few ps reolution, while at 1 GSPS, you
get like 15 ps. If you convolve 15 ps with 400 ps, you get 400.3 ps, which is not significantly worse than 400 ps.
Simon |
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Wed Feb 27 13:47:32 2013, Georg Winner, Chip Test - Cell Error
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When starting Chip Test in DRS Command Line Interface, I receive the following message:
Cell error on channel 1, cell 5: -154.4 mV instead 0 mV
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Wed Mar 6 13:08:03 2013, Stefan Ritt, Chip Test - Cell Error
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Georg Winner wrote:
When starting Chip Test in DRS Command Line Interface, I receive the following message: |
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Fri Nov 18 05:52:45 2016, Kurtis Nishimura, Channel offsets in GetTime()
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Hello,
I have a question about the GetTime() method in DRS.cpp. I understand how the DT values are applied for all channels, and I also understand
from the evaluation board manual that the timing of each channel is synchronized at sample 0, so samples should really be aligned from channel-to-channel |
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Mon Nov 21 14:13:32 2016, Stefan Ritt, Channel offsets in GetTime()
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Cell 700 is arbitrary. You can choose any cell to align the channels to each other. The only requirement is that it's always the same cell for each
event. Historically, Daniel chose cell #700 more or less arbitrary, but later we found out that this works with any cell. So for the publication we went
with cell #0 (and that's why we have t_ch,0 in the paper), but cell #700 was left in the code because of lazyness. Feel free to replace 700 with any |
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Sat Oct 22 13:24:20 2022, Phan Van Chuan, Channel Cascading Option in the 2048-bin
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Dear Stefan,
We are using DRS4 evaluation board version 5.1 and firmware version 30000 (as the picture attached). Now, I am in need one channel with length 2048
bin. However, I can't find the resistors R99, ... ,R106 on the hardware of evaluation board; it seems my DRS4 evaluation board doesn't use 2048 |
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Mon Oct 24 12:50:24 2022, Stefan Ritt, Channel Cascading Option in the 2048-bin
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The board is delivered in one or the other mode and not meant to be changed by the user, since this requires very delicate soldering which is not easy.
If you try anyhow, you loose the quarantee. You can send the board back to the manufacturer for the modification, but this costs quite some moeny.
Best regards, |
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Mon Aug 31 16:44:12 2020, Hans Steiger, Channel Cascading
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Dear All,
I have a board with Channel Cascading Option. I have the problem, that it seems to be impossible to run all 4 Channels simultaneously for digitizing
pulses. I can just run even or odd channels but not even and odd ones? If I run in combined option, My question: If a board comes with this combined option, |
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Mon Aug 31 17:17:30 2020, Stefan Ritt, Channel Cascading
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If you have a board with cascading option, it should show the "combined" option in the 2048-bin option enabled (not grayed), as in the
attached screen shot. If the 2048-bin option is all greyed out, the system does not recognize the cascading option. If your board has a sticker "2048
bin" and you still see the 2048-bin option greyed out, it might mean that a resistor on that board has been forgotten. If you do not see the "2048 |
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Thu Nov 14 11:39:06 2013, Schablo, Cascading of channels
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Hello, I want use cascading of channels for 2048 cell - SetChannelConfig(0,8,4), but i can't understand how . Please, help me. Where i can
dowload 2048_mode.ppt. (I found information about this file in DRS.cpp (3445 line "/ combine |
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Thu Nov 14 12:51:56 2013, Stefan Ritt, Cascading of channels
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Schablo wrote:
Hello, I want use cascading of channels for 2048 cell - SetChannelConfig(0,8,4), but i can't understand how . Please, help me. |
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Thu Nov 21 14:35:57 2013, Schablo, Cascading of channels
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Stefan Ritt wrote:
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Thu Nov 21 14:45:56 2013, Stefan Ritt, Cascading of channels
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Schablo wrote:
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Sat Feb 12 13:06:56 2022, Matias Senger, Cannot trigger on pulses, have to trigger on undershoot
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I am using the DRS4 board trying to measure pulses produced by an LGAD. I have no prior experience with this board, have just installed the `drsosc`
application and am exploring. I am experiencing some strange trigger behavior. Consider the following screenshot:
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Tue Feb 15 12:02:29 2022, Stefan Ritt, Cannot trigger on pulses, have to trigger on undershoot
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The trigger comparator is a ADCMP601 unit which requires a minimum pulse width of 3-4 ns. I see that your pulses are only 1-2 ns wide. You have to make
your pulses wider in order to trigger on them.
Stefan |