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ID
Date
Author
Subject
Text
770
Tue Aug 20 16:05:21 2019
Bill Ashmanskas
should one deassert DENABLE while writing the write-shift register?
241
Mon Apr 22 15:33:28 2013
Benjamin LeGeyt
effect of jitter/alignment between SRCLK and ADC clock
346
Fri May 16 14:04:47 2014
Benjamin LeGeyt
simultaneous writing and reading with region of interest mode?
132
Sat Oct 15 04:45:25 2011
Aurelien Bouvier
DRS4 eval board: readout rate
773
Fri Sep 13 15:27:41 2019
Arseny Rybnikov
Scaler / How to modify the firmware to change the scaler integration time
14
Wed Oct 14 23:53:05 2009
Armin Kolb
DRS_exam using USB Evaluation Board with OS X
294
Mon Sep 23 09:22:52 2013
Andrzej Rychter
Sampling Frequency: DRS4 eval board
296
Mon Sep 23 09:51:48 2013
Andrzej Rychter
Sampling Frequency: DRS4 eval board
397
Fri Feb 13 10:12:16 2015
Andrzej Grzeszczuk
drs4 and root
130
Fri Sep 16 22:06:07 2011
Andriy Zatserklyaniy
compilation error for version 4.0.0 on linux
307
Tue Nov 19 04:33:22 2013
Andriy Zatserklyaniy
DRSOsc at Mac OS X Mavericks
309
Tue Nov 19 21:49:37 2013
Andriy Zatserklyaniy
DRSOsc at Mac OS X Mavericks
168
Sat Jun 23 00:29:52 2012
Andrey Kuznetsov
triger for measuring time between pulses in channels
243
Wed May 8 06:07:52 2013
Andrey Kuznetsov
DRS4 v2.0 Eval Board running on higher versions of DRS Oscilloscope program
244
Wed May 8 19:50:01 2013
Andrey Kuznetsov
DRS4 installation on Windows 8 issues
279
Thu Jul 25 01:31:29 2013
Andrey Kuznetsov
Evaluation Board Behavior
289
Wed Aug 28 13:07:51 2013
Andrey Kuznetsov
Some bug fixes and questions
290
Thu Sep 5 10:01:00 2013
Andrey Kuznetsov
Some bug fixes and questions
291
Mon Sep 9 06:49:36 2013
Andrey Kuznetsov
Some bug fixes and questions
293
Wed Sep 11 02:41:28 2013
Andrey Kuznetsov
USB connection stops
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