| ID |
Date |
Author |
Subject |
Text |
 |
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112
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Sat Feb 19 17:25:29 2011 |
S S Upadhya | how to synchronize Sampling frequency of two evaluation boards | Dear sir,
We have two evaluation boards of
DRS4. We would like to use 8 inputs to be |
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113
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Sat Feb 19 22:46:35 2011 |
Stefan Ritt | how to synchronize Sampling frequency of two evaluation boards |
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114
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Mon Feb 21 08:10:31 2011 |
Stefan Ritt | how to synchronize Sampling frequency of two evaluation boards |
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115
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Mon Feb 21 12:42:33 2011 |
S S Upadhya | how to synchronize Sampling frequency of two evaluation boards |
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774
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Mon Oct 14 09:32:33 2019 |
Danyang | how to acquire the stop position with channel cascading | Hi Steffan,
In DSR4
DATASHEET Rev.0.9 Page13, there is |
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775
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Mon Oct 14 10:14:46 2019 |
Stefan Ritt | how to acquire the stop position with channel cascading | You first set A3-A0, on the next clock
cycle you issue pulses on srclk, and about
10ns after each clock pulse the output shows |
|
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776
|
Mon Oct 14 11:45:06 2019 |
Danyang | how to acquire the stop position with channel cascading | I tried the
logic in my designed board. The results
are shown in the picture: Srout keeps low |
|
|
777
|
Mon Oct 14 12:56:13 2019 |
Stefan Ritt | how to acquire the stop position with channel cascading | Note that you have to read out the Write
Shift Register only if you do channel cascading,
e.g. configuring the chip with 4x2048 bins |
|
|
778
|
Mon Oct 14 13:44:26 2019 |
Danyang | how to acquire the stop position with channel cascading | Yes, firstly I configured the chip
with 4x2048 bins by setting the Write Shift
Register to 01010101b， A3-A0 |
|
|
779
|
Mon Oct 14 15:27:09 2019 |
Stefan Ritt | how to acquire the stop position with channel cascading | If you configure the Write Shift Register
with 01010101b, then all you have to do after
a trigger is to set A3-A0 to 1101. The WSROUT |
|
|
780
|
Tue Oct 15 08:14:17 2019 |
Danyang | how to acquire the stop position with channel cascading | Thanks a lot. The problem is solved when
A3-A0 is set 1101 and srclk keeps low.
Best Regards, |
|
|
832
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Mon Sep 6 14:42:23 2021 |
Jiaolong | how to acquire the stop channel with 2x4096 cascading | Hi Steffan,
I have a question
about how to acquire the stop channel: |
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|
834
|
Sat Sep 18 15:47:50 2021 |
Stefan Ritt | how to acquire the stop channel with 2x4096 cascading | The problem must be on your side, since
the Write Shift Register readout works in
other applications with the DRS4 chip. So |
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|
Draft
|
Fri Nov 5 01:10:25 2021 |
Jiaolong | how to acquire the stop channel with 2x4096 cascading |
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|
850
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Fri Nov 5 01:12:10 2021 |
Jiaolong | how to acquire the stop channel with 2x4096 cascading | Thanks for your advice. The problem has
been solved by setting the srin again while reading
out from srout. |
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299
|
Wed Nov 6 11:53:28 2013 |
Dmitry Hits | flickering screen for drsosc | Hi,
I have install drs software on ASUS |
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300
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Wed Nov 6 12:25:31 2013 |
Stefan Ritt | flickering screen for drsosc |
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304
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Mon Nov 18 11:20:15 2013 |
Dmitry Hits | flickering screen for drsosc |
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63
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Tue Apr 13 10:45:18 2010 |
lorenzo neri | evaluation board used like a counter | Hi all
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64
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Tue Apr 13 13:12:43 2010 |
Stefan Ritt | evaluation board used like a counter |
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