Thanks for posting the plots. It really looks like the PLL is not working. I see two possible reasons: 1) The PLLEN bit in the configuration register is not set and 2) The REFCLK signal does not reach the chip. We had cases whrere people had a hard time to solder the DRS4 correctly due to the small pins. So if the REFCLK+ and REFCLK- signals have a poor connection, then the PLL of course won't work. Putting some more tin at the pins manually usually helps. Or remove the chip completely and try with another chip. In theory there is the possibility that the internal bond wire of the REFCLK signal has a bad connection, but we tested all chips we send out so we should have seen that. But trying with another chip cannot hurt in general. Next month I'm coming to the Weizman Institute for the ISOTDAQ shool. If you want we can meet there if you don't mind the 120 km drive from Haifa.
We have some measures to show (attached)
From the screen shots it can be seen that refck+ is not synchronized with Dtap (PLL not working correctly)
And Dspeed is going done to zero after some time.
In our system Dspeed is shorted to pllout.
So it looks like pllout do not pump the RC filter capacitors.
We tested various value of R and C's.
Also we checked that pllout is sorted to Dspeed.