surrey i forgot to update..
after carefully examining our VHDL we found out that there are brief times that we put A0-A3 in 1111
after making shore that a0-a3 never get 1111 value thae drs4 woks as expected.
The dtap toggols ok.
We can sample and read all the data channels.
So, putting A0-A3 value of 1111 even for very short period " confuse " the DRS and then it start to behave in a strange manner.
While I can understand 1., I'm puzzeled by 2.
If you put the chip in standby mode, the internal current sources are switched off, which of course make the domino wave non-functional. This is clearly stated in the data sheet.
Concerning the DMODE bit, we operate all (!) our chips with DMODE=1. Actually this is the default value. After a reset, all register bits are "1", which enables the PLL and causes DTAP to oscillate. If DMODE=1, the DTAP signal should toggle only once (!) since the domino loop is not closed. So the scope traces you showed previously are consistent with the standby mode, but not possible with ANY setting of DMODE.
We have resolve the problem, the Dtap is now working correctly.
There were two problems:
We are now setting the address bits to all zero. Failure
to do so result in Dtap stop toggling after several hundred milliseconds.
And not to 1.
Is this a known bug in the chip?
Only bay setting DMODE to zero we got the Dtap to work correctly.
The PLL locks after 1 milisec.
If we set it to one we get Dtap that stop toggling after several hundred milliseconds.
We have test it on two boards, they both worked in the same.
Never did we get a One shot Dtap.
Did you published a errata page to the drs4?