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Entry  Wed Dec 23 15:38:14 2015, mony orbach, Dtap stops toggling after 40msec 
    Reply  Wed Dec 23 15:48:42 2015, Stefan Ritt, Dtap stops toggling after 40msec 
       Reply  Thu Dec 24 10:51:31 2015, mony orbach, Dtap stops toggling after 40msec 
          Reply  Thu Dec 24 12:45:41 2015, Stefan Ritt, Dtap stops toggling after 40msec 
             Reply  Sun Dec 27 15:41:32 2015, mony orbach, Dtap stops toggling after 40msec Dtap-Denable.gifdtap-Danable2.gifDtap-refck.gifDtap-Dspeed.gif
                Reply  Mon Dec 28 11:05:15 2015, Stefan Ritt, Dtap stops toggling after 40msec 
                   Reply  Mon Dec 28 11:21:54 2015, mony orbach, Dtap stops toggling after 40msec 
                      Reply  Wed Dec 30 16:25:35 2015, mony orbach, Dtap stops toggling after 40msec 
                         Reply  Wed Dec 30 17:00:00 2015, Stefan Ritt, Dtap stops toggling after 40msec 
                            Reply  Thu Jan 14 14:00:26 2016, mony orbach, Dtap stops toggling after 40msec 
                               Reply  Thu Jan 14 14:11:06 2016, Stefan Ritt, Dtap stops toggling after 40msec 
Message ID: 473     Entry time: Thu Jan 14 14:00:26 2016     In reply to: 466     Reply to this: 474
Author: mony orbach 
Subject: Dtap stops toggling after 40msec 

surrey i forgot to update..

after carefully examining our VHDL we found out that there are brief times that we put A0-A3 in 1111

after making shore that a0-a3 never get 1111 value thae drs4 woks as expected.

The dtap toggols ok.

We can sample and read all the data channels.

So, putting A0-A3 value of 1111 even for very short period  " confuse " the DRS and then it start to behave in a strange manner.

 

mony

Stefan Ritt wrote:

While I can understand 1., I'm puzzeled by 2.

If you put the chip in standby mode, the internal current sources are switched off, which of course make the domino wave non-functional. This is clearly stated in the data sheet.

Concerning the DMODE bit, we operate all (!) our chips with DMODE=1. Actually this is the default value. After a reset, all register bits are "1", which enables the PLL and causes DTAP to oscillate. If DMODE=1, the DTAP signal should toggle only once (!) since the domino loop is not closed. So the scope traces you showed previously are consistent with the standby mode, but not possible with ANY setting of DMODE.

Stefan

mony orbach wrote:

Hi

We have resolve the problem, the Dtap is now working correctly.

There were two problems:

  1. After configuration we put the all address bits to one (standby mode)

We are now setting the address bits to all zero. Failure

to do so result in Dtap  stop toggling after several hundred milliseconds.

  1. The DMODE bit in contradiction to the data sheet should be set to 0

And not to 1.

 

Is this a known bug in the chip?

Only bay setting DMODE to zero we got the Dtap to work correctly.

The PLL locks after 1 milisec.

If we set it to one we get Dtap that stop toggling after several hundred milliseconds.

We have test it on two boards, they both worked in the same.

Never did we get a One shot  Dtap.

 

Did you published a errata page to the drs4?

 

Thanks, Mony

 

 

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