DRS4 Forum
  DRS4 Discussion Forum  Not logged in ELOG logo
Entry  Fri Feb 26 17:05:26 2021, Tom Schneider, Trouble getting PLL to lock 
    Reply  Fri Feb 26 17:59:14 2021, Stefan Ritt, Trouble getting PLL to lock 
       Reply  Fri Feb 26 18:33:52 2021, Tom Schneider, Trouble getting PLL to lock 
          Reply  Fri Feb 26 20:32:25 2021, Stefan Ritt, Trouble getting PLL to lock 
             Reply  Fri Feb 26 21:24:39 2021, Tom Schneider, Trouble getting PLL to lock 
                Reply  Fri Feb 26 22:12:58 2021, Stefan Ritt, Trouble getting PLL to lock 
                   Reply  Fri Feb 26 22:52:13 2021, Tom Schneider, Trouble getting PLL to lock 
                      Reply  Thu Mar 4 21:36:14 2021, Tom Schneider, Trouble getting PLL to lock 
                         Reply  Fri Mar 5 09:39:42 2021, Stefan Ritt, Trouble getting PLL to lock 
Message ID: 812     Entry time: Fri Feb 26 17:59:14 2021     In reply to: 811     Reply to this: 813
Author: Stefan Ritt 
Subject: Trouble getting PLL to lock 

I guess you mean "1 MHz clock at REFCLK+", and not CLKIN, there is no CLKIN, just a SRCLK, but that is someting else!

There could be many reasons why this is not working. It's hard for me to debug your board without actually having it in hands. So just some ideas:

- Supply a clean differential REFCLK, I never tried one end tied to VDD/2

- Is /RESET high?

- Is BIAS at roughly 0.7V?

- Is A0-A3 different from 1111, which puts the chip in standby

- Did you double check your loop filter?

The easiest usually is to start from a running evaluation board, then compare all pins 1:1 with your board.

Stefan

Tom Schneider wrote:

Hello,

I am working on a custom PCB design with the DRS4 chip, and I can't get the PLL to lock.  I'm feeding CLKIN with a 1MHz CMOS clock (REFCLK- tied to VDD/2), and I'm using the same loop filter as the eval board.  I see from the datasheet that the PLL is enabled by default, so I'm not writing anything to the config register on startup.  I am just driving DENABLE high approx. 100ms after startup and looking for the PLL lock bit to go high.  When I look at DTAP, I see a 3MHz signal.  Can anyone tell me what I'm doing wrong?

-Tom

 

ELOG V3.1.4-80633ba