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Entry  Fri Feb 26 17:05:26 2021, Tom Schneider, Trouble getting PLL to lock 
    Reply  Fri Feb 26 17:59:14 2021, Stefan Ritt, Trouble getting PLL to lock 
       Reply  Fri Feb 26 18:33:52 2021, Tom Schneider, Trouble getting PLL to lock 
          Reply  Fri Feb 26 20:32:25 2021, Stefan Ritt, Trouble getting PLL to lock 
             Reply  Fri Feb 26 21:24:39 2021, Tom Schneider, Trouble getting PLL to lock 
                Reply  Fri Feb 26 22:12:58 2021, Stefan Ritt, Trouble getting PLL to lock 
                   Reply  Fri Feb 26 22:52:13 2021, Tom Schneider, Trouble getting PLL to lock 
                      Reply  Thu Mar 4 21:36:14 2021, Tom Schneider, Trouble getting PLL to lock 
                         Reply  Fri Mar 5 09:39:42 2021, Stefan Ritt, Trouble getting PLL to lock 
Message ID: 819     Entry time: Fri Mar 5 09:39:42 2021     In reply to: 818
Author: Stefan Ritt 
Subject: Trouble getting PLL to lock 

That probably depends on the way your FPGA boots. If the SRCLK signal goes high after the SRIN - even a few ns - you might clock one or two zeros into the config register, thus disabling the PLL. Shame that I haven't thought of this before.

Stefan

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