Dear Dr. Stefan Ritt,
I am writing to express my sincere gratitude for your continued and prompt responses to our previous inquiries regarding the waveform truncation issue with the DRS4. Your advice and insights have been invaluable throughout this debugging process.
We have now preliminarily identified and resolved the problem. The key observation came when we powered the DRS4 from an independent supply: shortly after power‑up, with both DENABLE and DWRITE pulled low to GND, the VDD rail still drew an abnormally high current (approximately 1.8 A). This indicated that the DRS4 had been unintentionally activated into an abnormal state. While we confirmed with both an oscilloscope and a multimeter that the DENABLE and DWRITE pins remained at a valid low level, we suspected that the chip’s initialization was corrupted, preventing the internal registers from being loaded with their default values.
To address this, we manually reloaded the default register values via the FPGA. After this modification, the waveform truncation phenomenon completely disappeared.
Thus, we conclude that the root cause of the waveform truncation was improper initialization of the DRS4. Going forward, we will continue to improve the hardware conditions to ensure correct initialization of the chip.
Thank you once again, Dr. Ritt, for your active and generous support. We hope that the problem we encountered and the solution we found will be helpful to other DRS4 users and contribute to the healthy development of the DRS4 community.
| Stefan Ritt wrote: |
|
Not much I can say here. I know that the DRS4 works reliably, since we have an experiment here with 500 chips running since 5 years and we did not observer what you described. Therefore, it must be some subtle detail of your FPGA code or the voltage levels on your board. As I said, what I would do is to get the evaluation abord and copare signals 1:1.
Stefan
| QICHAOWU wrote: |
|
Dear Dr.Stefan
Thank you for your detailed response. Following your suggestion, I used an oscilloscope to observe the RSLOAD and SRCLK signals, and they conform to the readout timing described in the datasheet.
I can now confirm that the DRS4 occasionally fails to correctly update the stop position to cell 1023, or the stored waveform from cell 0 to the stop position is corrupted. As a result, part of the waveform comes from the most recent acquisition while the other part comes from an earlier one, causing the truncation I observed. This issue occurs with a certain probability—more than half of the acquisitions still yield complete, continuous waveforms.
Interestingly, when I use the same FPGA code and host software on the DRS4 evaluation board, no truncation occurs at all. I am currently comparing the behavior of the two setups from both hardware and software perspectives. Could you kindly provide some suggestions on further tests I could perform?
Thank you very much for your help.
Best regards,
Qichao Wu
| Stefan Ritt wrote: |
|
Actually looking at your waveforms again, I think I understand maybe your problem. You stop the DRS4 randomly, but your ROI readout mode does not really work. Seems like you always read from the first cell, or just from a wrong cell. Since your sine wave period is not a multiple of the readout window, you see a phase jump between the beginning of your sampling window and the end of your sampling window. The little spikes before and after the jump are normal, since the first and last samples of the DRS4 readout might have some offset. Check that your FPGA really uses RSLOAD to start the readout, and not the "full readout".
The evaluation board might really help you, since you can compare 1:1 all control signals with yours.
Stefan
| QICHAOWU wrote: |
|
Dear Dr. Stefan Ritt
I am writing to seek your advice regarding an issue I encountered while using the DRS4 chip in ROI (Region of Interest) readout mode to sample waveforms. My name is Qichao Wu, and I have been working with the DRS4 for waveform sampling.
In my setup, I input two identical sine waves (with a period of 250 ns and the same phase) into two different channels of the same DRS4 chip. Ideally, the waveforms acquired from both channels should completely overlap, as shown in Figure 1. However, I occasionally observe that the waveform from one of the channels is truncated. The truncated portion appears to originate from a different segment of the input signal, resulting in only partial overlap between the two channels. This phenomenon is illustrated in Figure 1. Additionally, there are instances where both channels exhibit truncation simultaneously, as depicted in Figure 2.
I have confirmed this issue by observing the truncated waveforms directly on an oscilloscope when the DRS4 is operated in ROI mode. Notably, the truncation points always occur near cell 0 and cell 1023 of the DRS4 switch array.
Could you kindly provide guidance on how to resolve or mitigate this issue? Any suggestions or insights you could offer would be greatly appreciated.
I look forward to your positive response and thank you in advance for your time and assistance.
Best regards,
Qichao Wu
|
|
|
|
|