The DRS4 gets into the "1.8A" state if DSPEED approaches like 0.7V. Then both inverters of the Domino chain are kind of open and a large current flows. In that state, the only way out is a power cycle.

It's however not clear to me how you get there. If DENABLE is low, this should be prevented. Most FPGAs however pull up their pins on power-on, and ony when configured, the pins go low according to the programming. Maybe it's the time during the FPGA boot which is your problem. Some FPGAs can be configured not to do this. I woulld recommend putting VDD analog, VDD digital, DSPEED, DENABLE, FPGA config ready, all on an oscilloscope and watch what happens during power on. The 1.8A state should be prevented by all means since it could damage the chip.

Stefan