In v4 board, which channel has best calibration ?
Should it be possible to simulate v5 board and read calibration values for v4 board by other method .. for example using external calibration signal source connected to all channels?
Is it needed to detach all input signals from EVM board during calibration ?( I see there are switches on channel inputs.)
Some comments: averager.h, averager.cpp are missing in windows v.5 sources (it should be copied from linux sources)
PF2014 and thank You for development new EVM 5 and new time precision.
In v4 board, actually no channel has a good calibration. The timing calibration is done with channel #9, which is hard connected to a (poor) clock. So the best you can get there is ~30 ps. In principle one can calibrate the V4 board with an external source. The problem there is to find a good sine wave oscillator (we have several expensive ones and only one was good enough), and that the software does not support this. You would have to write your own calibration code (where of course you can "recycle" the one from the V5 software.
Thanks for pointing out the missing averager.*, I will add it.
A quick question, what is the typical variation of the sampling capacitors in DRS4? Will this variation be significant to affect your sampling result?
The capacitors sample the input voltage, not the charge, so the actual size of the capacitors does not matter on first order (the variations might be in the order of 5%). A bigger effect is the variation of the analog switches in the front of the capacitors, which is about 15%. So the actual bandwidth each cell sees varies by maybe 20% (given by the R and the C), but this comes only into play when sampling steep edges.
Great to know this! Thanks~
Hi Dr. Stefan,
So the sampling capacitors store the input voltage instead of the charge. What about the readout circuits? I saw there is a buffer followed each sampling capacitor. Do you buffer the charge (like a charge sensitive amplifier) or the voltage? From Fig.12, 14 in datasheet, it seems most probably the readout is a charging or discharging of a capacitor. Could you please add some comments on this?
Hi Dr. Stefan,
The buffer buffers the voltage, not the charge. The curves in Fig. 12, 14 indicate that the voltage followers take some time until they settle.
I found that my collaborator bought 2 older version of evaluation board before.
They are the version 1.2 in plastics case with firmware 13191.
Can I upgrade the firmware from 13191 to 13279?
I'm wondering if the older version of evaluation board is working with firmware 13279.
I checked and there is no significant difference between the two revisions, so I would just leave it.
We are designing a waveform sampling board for Si strip array detector ,whose rise time is less than 10 ns, which makes we doubt whether the DRS4 can do more accurate than traditional charge integral circuit for charge measuring.
So we need to know what sort of detectors for physical experiment the DRS4 has been used in?
Can you give me some information? For example, Si strip array detector or CsI scintillator r ball detector ? PMT or APD ?
DRS4 is used for PMTs and APDs. The minimal rise/fall time which can be recorded with the DRS4 on the evaluation boards is about 0.8ns (see elog:84). Concerning charge measurement, it depends on your integration time. If your signal is for example 20ns and you sample with 5 GSPS, you get actually 100 samples. You digitize with 12 bits, but the S/N ratio is more like 11.5 bits. But since you have 100 samples, the accuracy of the measurement scales with sqrt(100)=10. So you have more like 11.5+3 bits = 14-15 bits, or a SNR of 20'000. Now your signal usually does not have an amplitude of 1V, will be more like 100mV or so, in which case your SNR goes to 2000. But this still gives you a resolution of 1/2000 = 0.5 per mille.
We did tests with a Ge detector for spectroscopy applications, where we used a shaping time of 2 micro seconds, both with traditional electronics and the DRS4, integrating the signal over 2 micro seconds. Both gave a resolution of about 0.4%, indicating that the resolution was not limited by the DRS but by the detector.
The diagram below is DRS4 output. Green is the output8+, blue is the output8-. Output8+ of the first channel is below the baseline. It is not right.
Others channel is suitable. I check the circuit , Hardware is no problem, so I want to konw where the FPGA code is wrong. what reason is caused? Thanks!
You are funny. Just by looking at a scope picture I should know what is wrong at your FPGA code. Unfortunately I'm not a magician. I looks to me like you have 11 channels in your diagram, although the chip has only 9. What I would recommend is to put some input to each channel one at a time, like a 10 MHz sine wave. You should then see that sine wave for the single channel at the output and can correlate input vs. output. Maybe your address bits are wrong or the chip has a soldering problem.