| ID |
Date |
Author |
Subject |
Text |
 |
|
740
|
Wed Feb 20 12:56:56 2019 |
Stefan Ritt | meg? | No idea. Maye some access problem. Have
you tried to start your program under an
admin account? |
|
|
739
|
Wed Feb 20 12:13:44 2019 |
Lev Pavlov | meg? | Great, drs_exam compiles without problems.
Now when you run the compiled file drs_exam
writes board not found, but drsosc and drscl |
|
|
738
|
Wed Feb 20 08:08:42 2019 |
Stefan Ritt | meg? | You have to change the path to libusb-1.0.lib
to the one where you installed it.
Stefan |
|
|
737
|
Wed Feb 20 08:03:04 2019 |
Lev Pavlov | meg? | Hey. Strange problem. Why does the compiler
refer there at all? Library installed drsosc
works |
|
|
736
|
Mon Feb 4 18:18:22 2019 |
Stefan Ritt | Different Distances between the sampling points | elog:361
|
|
|
735
|
Mon Feb 4 17:36:49 2019 |
Hans Steiger | Different Distances between the sampling points | Sorry.... but is there a solution or a
Root Macro, that reads the waveforms into
a Root-Tree? I simply can not work anymore |
|
|
734
|
Mon Feb 4 16:46:04 2019 |
Stefan Ritt | Different Distances between the sampling points | The sampling points are NOT equidestant,
they have varying bin widths of 150ps to
250ps at 5GS/s. That's due the way the |
|
|
733
|
Mon Feb 4 16:42:08 2019 |
Hans Steiger | Different Distances between the sampling points | Dear All,
with the older software for my
V5 Board i did not have the problem, that |
|
|
732
|
Sat Feb 2 10:10:22 2019 |
Stefan Ritt | Saving Rate (only 15Acq/s) | The reduction of rate is because you save
in XML format, which is an ASCII format,
so human readable, but takes long to write. |
|
|
731
|
Sat Feb 2 00:13:12 2019 |
Hans Steiger | Saving Rate (only 15Acq/s) | Dear All,
when I use my Evaluation Board |
|
|
730
|
Wed Jan 30 17:08:58 2019 |
Stefan Ritt | ROOT Macro for data acquired with the newest software | This one elog:361
should still work.
Stefan |
|
|
729
|
Wed Jan 30 08:02:25 2019 |
Stefan Ritt | DRS4 domino wave stability study | The Domino wave is most stable at 5 GSPS,
slowly degrades down to 3-2 GSPS, and at
1GSPS gets some significant jitter. This |
|
|
728
|
Wed Jan 30 06:51:37 2019 |
Saurabh Neema | DRS4 domino wave stability study | We have been using DRS4 IC in our design
for quite some time and it is giving good
performance. |
|
|
727
|
Tue Jan 29 14:43:44 2019 |
Abaz Kryemadhi | ROOT Macro for data acquired with the newest software | Hello,
Is there a root macro for decoding
binary data acquired with the newest software |
|
|
726
|
Thu Nov 8 12:02:34 2018 |
Davide Depaoli | Timing Issue | Thanks a lot for the quick response.
We will do as you suggest.
|
|
|
725
|
Thu Nov 8 11:54:33 2018 |
Stefan Ritt | Timing Issue | That's not a bug, but a feature of the DRS4
chip. The time bins have different values
by the properties of the chip. They are generated |
|
|
724
|
Thu Nov 8 11:44:35 2018 |
Davide Depaoli | Timing Issue | Hi,
We are using the DRS4 Evaluation Board as |
|
|
723
|
Thu Nov 8 09:57:26 2018 |
Stefan Ritt | Pi attenuator on eval board inputs? | The attenuator compensates for the gain
of the buffer which is slightly above one.
In addition, it serves as a "placeholder" |
|
|
722
|
Mon Nov 5 17:17:08 2018 |
Sean Quinn | Pi attenuator on eval board inputs? | Dear DRS4 team,
I am curious about this part of |
|
|
721
|
Wed Sep 26 19:21:03 2018 |
Stefan Ritt | Trigger OUT pulse width variable from 100 us up to 100 ms | In meantime I even updated the manual.
Stefan
|
|