ID |
Date |
Author |
Subject |
905
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Wed Oct 25 19:52:33 2023 |
John Westmoreland | WaveDREAM Design |
Stefan,
Oh, didn't realize that.
Thanks!
John
Stefan Ritt wrote: |
No. This is a proprietary design.
Best,
Stefan
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918
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Thu May 8 23:23:19 2025 |
Jonathan Bradshaw | Clarification of full channel readout |
Hi all
We're working on a new product using the DRS4 IC, and want to do a full readout from cell 0 (not just Region of Interest). I have a couple of questions I hope you can help me with:
- We plan to do a full readout sequence, starting at cell 0. Part of that sequence includes pulsing RSRLOAD and reading out the stop position as shown in v0.9 datasheet Figure 15. What should the DRS4 address bits A3..0 be set to for reading out the stop position? (I’m assuming it’s 1011 ‘Address Read Shift Register’)
- What is the output delay from the falling edge of SRCLK to valid data at SROUT?
- For channel readout, we pulse SRCLK to advance the read shift register. The diagram shown in v0.9 datasheet Figure 12 appears to show that the analog output is updated on the rising edge of SRCLK. Is this correct or have I misread the diagram? (Other shift register transfers are clocked on the falling edge
- The DRS4 v0.9 datasheet Figure 7 shows that the Configuration register is clocked on the falling edge of SRCLK. Just below that is the text “The new register content becomes immediately active at the eighth rising edge of the SRCLK signal.” Should that perhaps read ‘… the eighth falling edge of the SRCLK signal’?
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919
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Thu May 8 23:41:03 2025 |
Jonathan Bradshaw | Handling of Write Shift Register and Write Config Register |
Hi all
We're building a product which will use two different operating modes; firstly a long capcture using channel daisy chaining (2048 samples) and secondly a segmented capture (2 separate captures of 1024 samples each).
For the long capture, I'm looking to capture 2048 samples for 4 channels. Therefore I configure the Write Shift Register to 0b01010101 and the Write Config Register to 0b11111111. During capture with DWRITE=1 the Write Shift Register will update. Am I correct that once the capture is done and DWRITE=0, I can set A3..0 to 0b1101 and simply read the value of WSROUT to tell the difference?
For the segmented capture, I'm looking to capture 1024 samples for 4 channels on a first tirgger pulse, followed by 1024 samples for 4 channels on a second pulse. Therefore I configure the Write Shift Register to 0b11111111 and the Write Config Register to 0b01010101 and set DWRITE=0 to capture. After the first trigger I set DWRITE=0 and need to update the Write Config Register. Do I need to write in a whole 8 bits to the Write Config Register (i.e. 0b10101010), or can I just shift in a single new bit (value 0b0)? |
922
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Tue May 13 04:10:30 2025 |
Jonathan Bradshaw | Handling of Write Shift Register and Write Config Register |
Hi Stefan
Just so I'm 100% clear; is there no reliable way to perform 2 segmented captures with a single DRS4 IC?
While not a showstopper, this is a bit disappointing.
Stefan Ritt wrote: |
This is correct. Setting A0-A3 to 0b1101 multiplexes the Shift Write Register to SROUT, so you will either a "0" or a "1" depending on which of the two channels was written last.
Your segmented capture does unfortunately not work. Due to a bug in the silicon, the first (e.g. even) written channel gets half overwritten when you start sampling the second (odd) channel. I should remove that from the documentation.
Furthermore, reading the chip while writing on the "other side" introduces quite some additional noise. The recommended way to do simultaneous reading and writing is therefore to use two separate DRS4 chips and split the input signals to both chips, then read from one chip while writing to the other chip. This keeps the crosstalk at a minimum and both chips run at full performance.
Stefan
Jonathan Bradshaw wrote: |
Hi all
We're building a product which will use two different operating modes; firstly a long capcture using channel daisy chaining (2048 samples) and secondly a segmented capture (2 separate captures of 1024 samples each).
For the long capture, I'm looking to capture 2048 samples for 4 channels. Therefore I configure the Write Shift Register to 0b01010101 and the Write Config Register to 0b11111111. During capture with DWRITE=1 the Write Shift Register will update. Am I correct that once the capture is done and DWRITE=0, I can set A3..0 to 0b1101 and simply read the value of WSROUT to tell the difference?
For the segmented capture, I'm looking to capture 1024 samples for 4 channels on a first tirgger pulse, followed by 1024 samples for 4 channels on a second pulse. Therefore I configure the Write Shift Register to 0b11111111 and the Write Config Register to 0b01010101 and set DWRITE=0 to capture. After the first trigger I set DWRITE=0 and need to update the Write Config Register. Do I need to write in a whole 8 bits to the Write Config Register (i.e. 0b10101010), or can I just shift in a single new bit (value 0b0)?
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924
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Thu May 15 00:01:20 2025 |
Jonathan Bradshaw | Handling of Write Shift Register and Write Config Register |
All right, thank you for the clarification.
Stefan Ritt wrote: |
Yes this is correct. Anyhow, even if it would be working, you would not be happy with it. After having designed ~10 boards with the DRS4 chip, I learned the hard way that any digital activity on the board during the sampling phase is strictly forbidden. You see crosstalk up to 100's of mV in some cases (with a preamplifier on the board, 10-20mV without preamp). So rule #1 is to keep the board as "quite" as possible when sampling the input. If you would readout the odd channels of the DRS4 during sampling of the even channels, you would probably get so much crosstalk that the samples are almost unusable. Even if you would do this with two DRS4 chips next to each other, you have to make sure to put proper grounding between the two chips, and operate them completely independent (like each one has it's onw contol lines going to the FPGA). Designing such boards is not so easy and takes lots of experience from the layouter.
Stefan
Jonathan Bradshaw wrote: |
Hi Stefan
Just so I'm 100% clear; is there no reliable way to perform 2 segmented captures with a single DRS4 IC?
While not a showstopper, this is a bit disappointing.
Stefan Ritt wrote: |
This is correct. Setting A0-A3 to 0b1101 multiplexes the Shift Write Register to SROUT, so you will either a "0" or a "1" depending on which of the two channels was written last.
Your segmented capture does unfortunately not work. Due to a bug in the silicon, the first (e.g. even) written channel gets half overwritten when you start sampling the second (odd) channel. I should remove that from the documentation.
Furthermore, reading the chip while writing on the "other side" introduces quite some additional noise. The recommended way to do simultaneous reading and writing is therefore to use two separate DRS4 chips and split the input signals to both chips, then read from one chip while writing to the other chip. This keeps the crosstalk at a minimum and both chips run at full performance.
Stefan
Jonathan Bradshaw wrote: |
Hi all
We're building a product which will use two different operating modes; firstly a long capcture using channel daisy chaining (2048 samples) and secondly a segmented capture (2 separate captures of 1024 samples each).
For the long capture, I'm looking to capture 2048 samples for 4 channels. Therefore I configure the Write Shift Register to 0b01010101 and the Write Config Register to 0b11111111. During capture with DWRITE=1 the Write Shift Register will update. Am I correct that once the capture is done and DWRITE=0, I can set A3..0 to 0b1101 and simply read the value of WSROUT to tell the difference?
For the segmented capture, I'm looking to capture 1024 samples for 4 channels on a first tirgger pulse, followed by 1024 samples for 4 channels on a second pulse. Therefore I configure the Write Shift Register to 0b11111111 and the Write Config Register to 0b01010101 and set DWRITE=0 to capture. After the first trigger I set DWRITE=0 and need to update the Write Config Register. Do I need to write in a whole 8 bits to the Write Config Register (i.e. 0b10101010), or can I just shift in a single new bit (value 0b0)?
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631
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Fri Oct 13 03:39:01 2017 |
Jonathan Wapman | Raspberry Pi Connection Failure |
I am currently attempting to use a raspberry pi to connect to the DRS 4 board. I whenever I try to use the DRS Command Line TOol, Revision 21435 to connect to the drs board, I get the error
"musb_open: libusb_open() error -3"
"USB successfully scanned, but no boards found"
"No DRS Boards Found".
I successfully compiled the libusb driver before compiling the drs software 5.0.6, and installed all other listed packages in the install instructions. |
700
|
Wed Jun 13 13:23:17 2018 |
Julian Kemp | Maximum analog input voltage |
Dear all,
I have been wondering what the maximum analog input voltage for the DRS4 V5 evaluation board is. It came with a sticker indicating that it is "2.5V pk Max". On the other hand, when checking the manual (https://www.psi.ch/drs/DocumentationEN/manual_rev50.pdf), it says maximum allowed is 10V DC or even 30V for short pulses. I foresee an application where I cannot make sure that pulses stay below 2.5V, so the correct value will be quite important for me.
Best,
Julian |
702
|
Wed Jun 13 16:34:28 2018 |
Julian Kemp | Maximum analog input voltage |
Thank you! That solves my problem.
Stefan Ritt wrote: |
In principle the numbers in the manual are correct. But they relate to pulses of a certain length, because the input protection only works for DC voltage and for pulses which are not too long. Since we could not write this all on the label of the board, we decided to put there 100% safe value as a "warning" to people, meaning that if pulses are above 2.5V, they should look into the manual and read the details.
Stefan
Julian Kemp wrote: |
Dear all,
I have been wondering what the maximum analog input voltage for the DRS4 V5 evaluation board is. It came with a sticker indicating that it is "2.5V pk Max". On the other hand, when checking the manual (https://www.psi.ch/drs/DocumentationEN/manual_rev50.pdf), it says maximum allowed is 10V DC or even 30V for short pulses. I foresee an application where I cannot make sure that pulses stay below 2.5V, so the correct value will be quite important for me.
Best,
Julian
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401
|
Sun Apr 5 22:16:48 2015 |
Julien Wulf | DRS4 Evaluation Board Baseline/Voltage Calibration |
Hi,
I`m trying to calibrate my DRS4 evoluation board to an input range of 0-1V but it doesn`t work.
1) First I tried to calibrate it with the drsosc (version 5.0.3) Software. The -0.5V - 0.5V calibration works, but during the 0 - 1V calibration the Software crashes.
2) I also tried to calibrate the input range with a C++ DAQ Package (based on drs_exam). Here the code of the calibration:
....
b->SetInputRange(0.) (Center at 0 V )
b->CalibrateVolt(NULL);
....
Calibration Works
....
b->SetInputRange(0.5) (Center at 0.5 V )
b->CalibrateVolt(NULL);
....
Results in: Found 4096 stuck pixels on this board.
Did I do a mistake or is this a normal behaviour of the board? Also the board often crashes and I get a magic number 0000 after restarting the DAQ. Then the board needs to be restarted via pulling the plug. ( I ensured that I terminate the USB connection before I close the program with "delete drs"). Is there a possibility to avoid this error?
My OS: Ubuntu 14.04 LTS.
Ciao,
Julien |
916
|
Thu Mar 27 15:53:10 2025 |
Justin Tabbett | Noisy counts with adapted drs_exam.cpp |
Greetings,
I have adapted the drs_exam.cpp to allow for a user input number of channels and trigger levels.
The program mostly works well, however there are counts which form a noise peak, imposed on the regular channel response.
To illustrate, I acquired 10,000 counts (measuring peak to peak) with the drsosc, and with my adapted script, with two channels and OR trigger logic.
Is there something missing in my code that could explain the cause of this noise peak? I have attached the .cpp file.
Many thanks,
Justin |
784
|
Thu May 21 07:18:48 2020 |
Keita Mizukoshi | DRS4 Evaluation board control tool 'drscl' with macro file |
Dear experts,
I would like to use DRS4 evaluation board as DAQ system for small, table-top experiment.
I need waveforms capture as binary file on some trigger based on command line without GUI.
I found `drscl` tool in official software, but it require interactive command. I'd rather use static macro or so on to control DAQ as same behaviour in each time.
I guess, experts are thinking users should develop DAQ code by themselves for their experiment specifically, but my request is very common so someone has already developed these tool.
Best regards,
Keita |
785
|
Thu May 21 07:38:05 2020 |
Keita Mizukoshi | Type check at DOFrame.h in official software |
Hi,
I've failured to compile official software. The cause is the following line.
DOFrame.h L.111 bool GetRefclk() { return m_refClk > 0; }
m_refClk is pointer to bool. I guess these line is for null-check of the pointer.
Can I replace the following line as
bool GetRefclk() { return m_refClk != nullptr; }
?
The latest compilers may not accept C-style check.
My compiler version is
Apple clang version 11.0.3 (clang-1103.0.32.59)
Target: x86_64-apple-darwin19.4.0
Thread model: posix
InstalledDir: /Applications/Xcode.app/Contents/Developer/Toolchains/XcodeDefault.xctoolchain/usr/bin
Best regards,
Keita |
789
|
Mon May 25 03:36:12 2020 |
Keita Mizukoshi | DRS4 Evaluation board control tool 'drscl' with macro file |
Thank you very much. That is what I wanted.
Stefan Ritt wrote: |
There is an example program in the distribution under software/drscl/drs_exam.cpp which is a stand-alone program to do what you need. It uses the C library coming with the distribution. It configureres the board, defines a trigger, and then writes a few waveforms into a file. You can use it as a starting point for your development. If you need any other language, you have to develop bindings to the C library.
Stefan
Keita Mizukoshi wrote: |
Dear experts,
I would like to use DRS4 evaluation board as DAQ system for small, table-top experiment.
I need waveforms capture as binary file on some trigger based on command line without GUI.
I found `drscl` tool in official software, but it require interactive command. I'd rather use static macro or so on to control DAQ as same behaviour in each time.
I guess, experts are thinking users should develop DAQ code by themselves for their experiment specifically, but my request is very common so someone has already developed these tool.
Best regards,
Keita
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837
|
Thu Oct 14 15:19:00 2021 |
Keita Mizukoshi | livetime (or deadtime) of DRS4 evaluation board |
Dear experts,
I would like to use the DRS4 evaluation board for actual physics experiment.
I made a CUI script based on the drs_exam, https://github.com/mzks/drs4_tools/blob/main/build/source/drscmd.cpp.
In this framework, how can we obtain DAQ livetime (or deadtime)?
Has some function already provided to evaluate them from firmware?
Best regards,
Keita |
839
|
Thu Oct 14 18:03:52 2021 |
Keita Mizukoshi | livetime (or deadtime) of DRS4 evaluation board |
Thank you very much for your response.
Excuse me for my very stupid confirmation.
If I take N events finally and the hardware scaler value is M, the livetime is realtime*(N/M). Is this correct?
Stefan Ritt wrote: |
The one thing you can do easily is to look at the scaler values. If one channel counts all physical events, and you have all read out events, then the ratio give you the live/deadtime. The hardware scalers also keep running during the DRS readout.
Stefan
Keita Mizukoshi wrote: |
Dear experts,
I would like to use the DRS4 evaluation board for actual physics experiment.
I made a CUI script based on the drs_exam, https://github.com/mzks/drs4_tools/blob/main/build/source/drscmd.cpp.
In this framework, how can we obtain DAQ livetime (or deadtime)?
Has some function already provided to evaluate them from firmware?
Best regards,
Keita
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841
|
Fri Oct 15 06:15:53 2021 |
Keita Mizukoshi | livetime (or deadtime) of DRS4 evaluation board |
Thank you very much.
Stefan Ritt wrote: |
I would say not exactly, but it's a good approximation.
Keita Mizukoshi wrote: |
Thank you very much for your response.
Excuse me for my very stupid confirmation.
If I take N events finally and the hardware scaler value is M, the livetime is realtime*(N/M). Is this correct
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866
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Tue Mar 1 19:03:37 2022 |
Keita Mizukoshi | Scaler issue to evaluate live time |
Hi. I'm trying to evaluate livetime of the evaluation board with the hardware scaler. I'm facing a strange issue.
I took the rate with the function, DRS->GetScaler(int channel).
I guess that channels 0--3 mean the rate for the channel, and channel 4 means the counter of the trigger.
I took the 1,000 pulses generated by a pulse generator with 50 Hz.
The scaler values are ~ 39.83, not 50.
The timestamp difference between the initial event and the final event is 19.98 seconds.
1000/19.98 ~ 50, thus, the evaluation board took the pulses with enough livetime.
Can we believe the scaler value for the livetime evaluation? |
870
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Fri Mar 4 03:55:33 2022 |
Keita Mizukoshi | Scaler issue to evaluate live time |
Thank you very much for your explanation.
I would like to show you a pulse example ('black line is the threshold).
Still, pulse generator rate and DRS4 rate are a bit different more than 10 Hz.
Stefan Ritt wrote: |
The scalers are read out 10x per seconds, so they have an accuracy of 10 Hz. I tried a 50 Hz pulser, and measured 40 Hz, I tried 52 Hz and measured 50 Hz. This is about what you can expect.
The scaler rate is measured after the discriminator of the trigger, so the trigger level also affects the scaler reading. If you have a 100 mV pulse and your threshold is 200 mV, your scaler rate drops to zero. That can be seen best with the DRSOsc and sliding the trigger value. If you have a 50 Hz pulse with narrow (< us) pulses, things are fine. But if you use a 50 Hz square wave, then you get distorted signals due to the AC coupling which can also be confusing. See for example here: https://www.daqarta.com/dw_gg0o.htm
Keita Mizukoshi wrote: |
Hi. I'm trying to evaluate livetime of the evaluation board with the hardware scaler. I'm facing a strange issue.
I took the rate with the function, DRS->GetScaler(int channel).
I guess that channels 0--3 mean the rate for the channel, and channel 4 means the counter of the trigger.
I took the 1,000 pulses generated by a pulse generator with 50 Hz.
The scaler values are ~ 39.83, not 50.
The timestamp difference between the initial event and the final event is 19.98 seconds.
1000/19.98 ~ 50, thus, the evaluation board took the pulses with enough livetime.
Can we believe the scaler value for the livetime evaluation?
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508
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Fri Apr 15 12:58:46 2016 |
Konstantin Gusev | DRS4 purchase information |
Hi,
I can't contact with Anita Van Loon about DSR4 chip's price and delivery.
Did you still sell it? Can you provide me this information? |
890
|
Tue Sep 27 10:17:58 2022 |
Kunal Shinde | Required Firmware for DRS4 Evaluation Board Version 2.0 |
Hi, I am working on an old DRS4 board Version "2.0" with firmware revision "13191", I was unable to find this specific firmware source files ("VHDL source code"), please help me where could I find this or send me the required.
Regards,
Kunal |