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ID Date Authorup Subject
  703   Tue Jun 19 06:42:23 2018 Phan Van ChuanThe data acquisition speed

Dear Stefan,

We are using an DRS4 board V5.1 for building a metering system for the scintillator detector by a Labview program. The program was built based on the functions in DRS.cpp and it reads data from channel 0 very well (Fig 1). Now, I am having a problem with the data acquisition from DRS4 board. The data acquisition speed on this program is only about 30-50 Acq / s, while using the DRS Oscilloscope that of about 300-400 Acq / s.

When the program was installed with fDominoMode = 0 and fDominoActive = 0, the data acquisition speed was about 300-400 Acq / s. However, the waveform is inaccurate.

I do not know if I installed the wrong function! Can you show me how to solve this problem?

In the Labview program, functions (corresponding to functions in DRS.cpp) are called with the following parameters:

 

InitFPGA();

SetMultiBuffer(0);

fROFS = 1.6;              // differential input range -0.5V ... +0.5V

fRange = 0;

SetDAC(fDAC_ROFS_1, fROFS);

 fCommonMode = 0.8;        // 0.8V +- 0.5V inside NMOS range

SetDAC(fDAC_CALP, fCommonMode);

SetDAC(fDAC_CALN, fCommonMode);

SetDAC(fDAC_BIAS, 0.70);

/* set default number of channels per chip */

SetChannelConfig(0, fNumberOfReadoutChannels - 1, 8);

// set ADC clock phase

      fADCClkPhase = 0;

      fADCClkInvert = 0;

   // default settings

fMultiBuffer = 0;

   fNMultiBuffer = 0;

   fDominoMode = 1;

   fReadoutMode = 1;

   fReadPointer = 0;

   fTriggerEnable1 = 1;

   fTriggerEnable2 = 0;

   fTriggerSource = 0;

   fTriggerDelay = 0;

   fTriggerDelayNs = 0;

   fSyncDelay = 0;

   fNominalFrequency = 1;

   fDominoActive = 1;

// load calibration from EEPROM

ReadCalibration();

...

SetDominoMode(fDominoMode);

   SetReadoutMode(fReadoutMode);

   EnableTrigger(fTriggerEnable1, fTriggerEnable2);

   SetTriggerSource(fTriggerSource);

   SetTriggerDelayPercent(0);

   SetSyncDelay(fSyncDelay);

   SetDominoActive(fDominoActive);

   SetFrequency(fNominalFrequency, true);

   SetInputRange(fRange);

SelectClockSource(0); // FPGA clock

// disable calibration signals

   EnableAcal(0, 0);

   SetCalibTiming(0, 0);

   EnableTcal(0);

   // got to idle state

   Reinit();

 

////////

SetFrequency (1,false);

settranspmode (1);

setinputrange(0);

EnableTcal (0,-,-);

EnableTrigger(1, 0);

SetTriggerSource(0);

SetTriggerLevel(0);

SetTriggerPolarity(false);

SetTriggerDelayNs(512);

 

// in loop of read data from DRS4:

 {

StartDomino();

while (b->IsBusy());

TransferWaves(0, 8);

GetTime(0, 0, b->GetTriggerCell(0), time_array[0]);

GetWave(0, 0, wave_array[0]);

}

 

Thank you very much!

Best Regards,

Chuan

 

 

  705   Tue Jun 19 12:54:51 2018 Phan Van ChuanThe data acquisition speed

Thank Stefan Ritt, I added the SoftTrigger() just after StartDomino(), so now, The data acquisition speed the same speed as in the DRS oscilloscope. I have misunderstood the "auto" trigger on an oscilloscope as setting SetTriggerLevel (0).
Thank so much!

Phan Van Chuan

Phan Van Chuan wrote:

Dear Stefan,

We are using an DRS4 board V5.1 for building a metering system for the scintillator detector by a Labview program. The program was built based on the functions in DRS.cpp and it reads data from channel 0 very well (Fig 1). Now, I am having a problem with the data acquisition from DRS4 board. The data acquisition speed on this program is only about 30-50 Acq / s, while using the DRS Oscilloscope that of about 300-400 Acq / s.

When the program was installed with fDominoMode = 0 and fDominoActive = 0, the data acquisition speed was about 300-400 Acq / s. However, the waveform is inaccurate.

I do not know if I installed the wrong function! Can you show me how to solve this problem?

In the Labview program, functions (corresponding to functions in DRS.cpp) are called with the following parameters:

 

InitFPGA();

SetMultiBuffer(0);

fROFS = 1.6;              // differential input range -0.5V ... +0.5V

fRange = 0;

SetDAC(fDAC_ROFS_1, fROFS);

 fCommonMode = 0.8;        // 0.8V +- 0.5V inside NMOS range

SetDAC(fDAC_CALP, fCommonMode);

SetDAC(fDAC_CALN, fCommonMode);

SetDAC(fDAC_BIAS, 0.70);

/* set default number of channels per chip */

SetChannelConfig(0, fNumberOfReadoutChannels - 1, 8);

// set ADC clock phase

      fADCClkPhase = 0;

      fADCClkInvert = 0;

   // default settings

fMultiBuffer = 0;

   fNMultiBuffer = 0;

   fDominoMode = 1;

   fReadoutMode = 1;

   fReadPointer = 0;

   fTriggerEnable1 = 1;

   fTriggerEnable2 = 0;

   fTriggerSource = 0;

   fTriggerDelay = 0;

   fTriggerDelayNs = 0;

   fSyncDelay = 0;

   fNominalFrequency = 1;

   fDominoActive = 1;

// load calibration from EEPROM

ReadCalibration();

...

SetDominoMode(fDominoMode);

   SetReadoutMode(fReadoutMode);

   EnableTrigger(fTriggerEnable1, fTriggerEnable2);

   SetTriggerSource(fTriggerSource);

   SetTriggerDelayPercent(0);

   SetSyncDelay(fSyncDelay);

   SetDominoActive(fDominoActive);

   SetFrequency(fNominalFrequency, true);

   SetInputRange(fRange);

SelectClockSource(0); // FPGA clock

// disable calibration signals

   EnableAcal(0, 0);

   SetCalibTiming(0, 0);

   EnableTcal(0);

   // got to idle state

   Reinit();

 

////////

SetFrequency (1,false);

settranspmode (1);

setinputrange(0);

EnableTcal (0,-,-);

EnableTrigger(1, 0);

SetTriggerSource(0);

SetTriggerLevel(0);

SetTriggerPolarity(false);

SetTriggerDelayNs(512);

 

// in loop of read data from DRS4:

 {

StartDomino();

while (b->IsBusy());

TransferWaves(0, 8);

GetTime(0, 0, b->GetTriggerCell(0), time_array[0]);

GetWave(0, 0, wave_array[0]);

}

 

Thank you very much!

Best Regards,

Chuan

 

 

 

  895   Sat Oct 22 13:24:20 2022 Phan Van ChuanChannel Cascading Option in the 2048-bin

Dear Stefan,
We are using DRS4 evaluation board version 5.1 and firmware version 30000 (as the picture attached). Now, I am in need one channel with length 2048 bin. However, I can't find the resistors R99, ... ,R106 on the hardware of evaluation board; it seems my DRS4 evaluation board doesn't use 2048 bins per channel.
Our question is, can we repair this hardware to read 2048 bins/channel? if that is possible please let me know what to add on hardware/software of DRS4 evaluation.
Best regards.
Phan Van Chuan.

  889   Wed Sep 7 10:13:41 2022 Prajjalak ChattopadhyayRegister status after reset

What are the default register statuses after DRS4 gets reset?

  873   Mon Mar 7 13:38:03 2022 Radoslaw MarcinkowskiProblems with DRS4 Evaluation Board after Windows 10 upgrade - share of experiences

Dear DRS4 Users,

I would like to share my expireinces with using of DRS4 Evaluation Board software (oscilloscope) after upgrade of Windows 10.

I had Windows 10 (Enterprise) in version from ~2016. It was working fine with DRS4 Scope software. Due to the company policy, Windows was upgraded to the newer version (2019). Since this time the board was not recognized any more as DRS4 Evaluation Board, both by Windows and DRS4 Scope standard software. Changing USB sockets did not help at all. I installed once more time Zadig USB driver (suggested by https://www.psi.ch/en/drs/software-download), no Admistrator rights were needed. It took long time, about 10 minutes or more, it suggested restart in the meantime, and finally noticed that ... installation failed! Even that, DRS4 software started to recognize the board without the problem even without reboot. Let me notice that all users on this machine can use the DRS4 software even if installation was done by non-administrator user.

 

Regards,

Radek

  395   Fri Jan 16 13:29:05 2015 Rainer HentgesMac OSX Yosemite 10.10
Hello,

I can compile version 5.0.3 of DRS4sc on Mac OSX 10.0 without errors but when I want to execute the program I get the following error:

[home]$ ./DRSOsc
DRSOsc(48068,0x7fff7ac5e300) malloc: *** error for object 0x7f88d9434a80: incorrect checksum for freed object - object was probably 
modified after being freed.
*** set a breakpoint in malloc_error_break to debug

Is this a known error? Will it be fixed in the next release?
  572   Mon Nov 28 22:28:34 2016 Randall GladenLong timing between two channels

I don't believe I fully understand how the timing works between multiple channels on DRS4 board, even after reading the manual, but I am hoping to measure a time difference between two channels longer than 1024/sampling rate. So far, I have written a program in Matlab to extract timing and voltage information from the binary file to find the time difference between two channels that are set with the AND trigger logic and appear within approximately 80 ns of each other at a sampling rate of 1 GSPS. This works as intended, but I would now like to try to measure time differences of anywhere between 50 ns and several ms within a single spectrum. Since this is out of the range of only 1024 channels above 1GSPS, is it possible for the board to keep track of the time between two trigger pulses that occur at time differences longer than 1024/sampling rate?

Thank you very much for your help, and if I am severely misunderstanding how the board works, please forgive my ignorance and feel free to correct me,

~Randall

Edit: I forgot to mention that I am collecting the data using the provided DRS4 Oscilloscope software.

  145   Thu Jan 26 09:12:03 2012 Ravindra Raghunath ShindeDRS4 Rev2.0 for analog pulse counting

Hello,

We are using DRS4 Rev.2.0 board.

We want to measure number of pulses generated  by charge particle detector. These negative going analog pulses are very fast having rise time about 2nS.

We want keep threshold level to -20mV. We expected pulse rate to be about 100 to 200 Hz.

I need help to implement this in  current DRS board with  dead time free operation.

 

  147   Thu Jan 26 09:44:34 2012 Ravindra Raghunath ShindeDRS4 Rev2.0 for analog pulse counting

Stefan Ritt wrote:

Ravindra Raghunath Shinde wrote:

Hello,

We are using DRS4 Rev.2.0 board.

We want to measure number of pulses generated  by charge particle detector. These negative going analog pulses are very fast having rise time about 2nS.

We want keep threshold level to -20mV. We expected pulse rate to be about 100 to 200 Hz.

I need help to implement this in  current DRS board with  dead time free operation.

 

If you just want to count pulses, you do not need a DRS board. Just use a discriminator and a counter, that's much simpler. The DRS board is not dead time free. 

 Thanks for your prompt reply.

Along with pulse rate  we also want see pulse shape as well as charge measurements. That is why we are exploring this option with our existing DRS Set-up.

 

  149   Thu Jan 26 10:05:57 2012 Ravindra Raghunath ShindeDRS4 Rev2.0 for analog pulse counting

Stefan Ritt wrote:

Ravindra Raghunath Shinde wrote:

Stefan Ritt wrote:

Ravindra Raghunath Shinde wrote:

Hello,

We are using DRS4 Rev.2.0 board.

We want to measure number of pulses generated  by charge particle detector. These negative going analog pulses are very fast having rise time about 2nS.

We want keep threshold level to -20mV. We expected pulse rate to be about 100 to 200 Hz.

I need help to implement this in  current DRS board with  dead time free operation.

 

If you just want to count pulses, you do not need a DRS board. Just use a discriminator and a counter, that's much simpler. The DRS board is not dead time free. 

 Thanks for your prompt reply.

Along with pulse rate  we also want see pulse shape as well as charge measurements. That is why we are exploring this option with our existing DRS Set-up.

 

I understand that. But still the board has some dead time which is dominated by the USB data transfer speed.

There is a way to perform the counting dead time free, but that requires the V4 board, which has a hardware comparator on all four channels (The V2 board has only one comparator and a multiplexer). The output of these comparators go directly to the FPGA, which can then trigger on these signals. In principle one could implement a hardware counter in the FPGA, which works practically dead time free. But this requires a new firmware which has to be written. Either you do it yourself using the Xilinx development tools, or you wait until I find some time to implement this, which could take a couple of weeks or even months.

Best regards,

Stefan 

 Thank you very much.

With regards,

Ravindra R. Shinde

  792   Tue Jul 28 22:40:44 2020 Razvan Stefan Gorneano board found

I have a very similar problem, the command line doesn't work but the oscilloscope program does! Tried to fix it using Zadig driver update. Using Windows 7.... 

DRS command line tool, Revision 21435
Type 'help' for a list of available commands.

USB successfully scanned, but no boards found
No DRS Boards found

For completion, I just tested that the test program gives the same error message

C:\Program Files (x86)\DRS\bin>.\drs_exam.exe
USB successfully scanned, but no boards found
No DRS4 evaluation board found

 

Stefan Ritt wrote:

"dynamic" or "static" does not matter, as long as you don't use your program on another computer. I have no more idea about the "no board found" problem. It works ok on all computers I tried at our lab.

Stefan

Lev Pavlov wrote:

 

Hello. When compiling drs_exam, do you need to use a "static "version of usblib or a "dynamic" version?"The problem with "no board found" is not solved. Thanks for your help.

Lev

 

  616   Thu Jun 8 14:26:23 2017 Rebecca SchmitzAND Trigger problems with 2-3 channels

Hello,

I work with the DRS4 Evaluation Board V5 and I have a problem with the software.

I have a problem with the AND trigger setting.
For this I have chosen the AND trigger function. However, when ONE channel senses an impulse, it triggers. I'm not able to see signals in the other channels, which I selected for the coincidence.

What is the cause of this? Maybe the time window?

I would like to measure a coincidence with two or three random channels. Is it possible?

Thanks for the help.

Rebecca

  618   Fri Jun 9 09:44:33 2017 Rebecca SchmitzAND Trigger problems with 2-3 channels

Hello,

It seems that a coincidence with two fixed channels suddenly works. I don't know why.

Screenshot 1 shows the trigger settings for the coincidence with two channels.
Screenshot 2 shows the oscilloscope surface.
Screenshot 3 shows the configuration. In the background there is a coincidence with three channels.

In contrast to the coincidence with two channels this doesn't look good.

Rebecca

Stefan Ritt wrote:

Can you post a screenshot where I can see the channel waveforms, the configuration and the trigger settings?

Stefan

Rebecca Schmitz wrote:

Hello,

I work with the DRS4 Evaluation Board V5 and I have a problem with the software.

I have a problem with the AND trigger setting.
For this I have chosen the AND trigger function. However, when ONE channel senses an impulse, it triggers. I'm not able to see signals in the other channels, which I selected for the coincidence.

What is the cause of this? Maybe the time window?

I would like to measure a coincidence with two or three random channels. Is it possible?

Thanks for the help.

Rebecca

 

 

  454   Thu Nov 26 18:59:27 2015 Robert AdamsSaving histogram data

I would really love to be able to save histogram data, though I have not been able to do this. I could take a screenshot and extract the data from an image, but would prefer to avoid this if there is a simpler way... possibly I have overlooked something obvious? Thanks very much for any advice or tips.

  906   Thu Feb 22 01:21:11 2024 Rod McInnisSimulation of FPGA

Hello:

A bit of background:  I am working on a project that is utilizing the DRS4 Evaluation board as a prototype platform for a dedicated, special use capture. We will only be utilizing one channel of the ADC capture, and the 1024 samples is more than enough. 

What I will need to do, however, is do some preprocessing on the incoming ADC data, running some calculation on the fly, possibly some filtering and other transformations before putting the data into the FPGA block memory for transfer to the host via the Cypress USB interface. I will be modifying the "drs4_eval5" VHDL file and doing a new FPGA build.

It will be essential that I be able to simulate this, from the ADC input to the data flow to the Cypress chip. I have "eval board files" which includes the VHDL source files, Xilinxe ISE project files and some very basic simulation testbenches.

Unfortunately, the simulation testbenches call out a "drs4_eval1" module while the Xilinx project uses a "drs4_eval5" module, and the module ports are a little different. I think I can work around that, however.  I have run the simulatilon "drs4_eval1_tb", which does a simple write to a Control Register. I need to expand this simulation so that it will initiate a full capture and then transfer the data from the RAM to the Cypress chip.

What I am most confused about is how the Cypress chip sucks out the data from the FPGA block ram. I would expect it to use a burst mode data transfer rather than the cumbersom CSR read/write, but I haven't found any documentation on how this interface works. 

Q1: Is there a simulation testbench file available that does the 1024 sample data transfer?

Q2: Is there a waveform diagram that shows the protocol / signal handshake between the FPGA and Cypress chip for this data transfer?

 

Thank you

Rod McInnis

 

 

  666   Wed Mar 7 22:49:38 2018 Rodrigo Trindade de MenezesRunning drs_example.cpp

Hello,

We have been using the DRS4 evaluation board (S/N 2636) that works with the scope application. However we are trying to run the DRS4 evaluation board remotely by modifying the drs_exam.cpp to acquire and store data continuously.

We compiled the DRS_example.cpp without the wxWidgets but when we try to run the program, it appears to trigger on nonsense.  The program appears to not be sensitive to the trigger threshold (although for very large trigger threshold it gets stuck in a waiting mode).  Is there a way to ensure that the "normal" trigger mode is set?  We are worried that the auto mode is running.  Otherwise, not sure why the program is triggering on nonsense.  By the way, it does not work with the wxWidgets compiled either so we are worried that there is an additional flag that needs to be set. The routine does not appear to conduct a calibration -- is this not necessary?

Another issue that we are having is with the data set stored on the .txt file looks incorrect.  The time channel stops at 200 (but we think it should go up to 1024). In addition, the voltage channel appears to hover around small values near zero (as if triggering on noise).  The output file appears this way even when we change the threshold to much higher values.  It suggests that the trigger threshold is not actually being set? There are events where the output voltage appears to oscillate through huge negative and positive values too.  So not sure what's going on. 

Thanks!

Rodrigo

  667   Thu Mar 8 22:54:20 2018 Rodrigo Trindade de MenezesRunning drs_example.cpp

We found a way to solve the previous problem, but right now when we try to set the input range only -0.5 to 0.5 is working. When we set the function "SetInputRange(0.5)" for 0 to 1V the output is all zeros and with  "SetInputRange(0.45)" we just get all the outputs -49.9mV. What does that means? How to fix?

odrigo Trindade de Menezes wrote:

Hello,

We have been using the DRS4 evaluation board (S/N 2636) that works with the scope application. However we are trying to run the DRS4 evaluation board remotely by modifying the drs_exam.cpp to acquire and store data continuously.

We compiled the DRS_example.cpp without the wxWidgets but when we try to run the program, it appears to trigger on nonsense.  The program appears to not be sensitive to the trigger threshold (although for very large trigger threshold it gets stuck in a waiting mode).  Is there a way to ensure that the "normal" trigger mode is set?  We are worried that the auto mode is running.  Otherwise, not sure why the program is triggering on nonsense.  By the way, it does not work with the wxWidgets compiled either so we are worried that there is an additional flag that needs to be set. The routine does not appear to conduct a calibration -- is this not necessary?

Another issue that we are having is with the data set stored on the .txt file looks incorrect.  The time channel stops at 200 (but we think it should go up to 1024). In addition, the voltage channel appears to hover around small values near zero (as if triggering on noise).  The output file appears this way even when we change the threshold to much higher values.  It suggests that the trigger threshold is not actually being set? There are events where the output voltage appears to oscillate through huge negative and positive values too.  So not sure what's going on. 

Thanks!

Rodrigo

 

  334   Thu Apr 10 14:45:12 2014 Roman GredigDRS4 Evalboard V5 with Windows7Pro64bit
Dear Stefan

I am trying to use the DRS4 eval board on a Windows7 machine. Unfortunately I get an error message saying "No DRS 
board found". But I can see the DRS board in the device manager with the proper driver loaded. Is there any known 
problem with win7?

I am using windows7 professional (SP1) with the drs software 5.0.1.

Cheers,
Roman

PS: Everything is working on my mac. But not under windows7.
  353   Thu Jun 12 12:40:03 2014 Roman GredigDRS eval bord v5 Timing
Dear Stefan

I have two questions concerning the best time resolution with the DRS V5 eval board.
a) Calibration:
I am using 4 boards daisy chained. To achieve optimal time resolution I did first a voltage calibration and right afterwards a time calibration. For all 
boards after the master I am not sure how to do it.
After setting the flag "Configure multi-board daisy-chain" in the config menu, all the slave boards set the flag "use external reference clock".  By 
hitting the voltage calibration button, the slave boards unset this flag. Is it true, that I have to re-set this before doing the time-calibration right 
afterwards?


b) getting the right times in binary format:
To get the time out of the time width (i.e. the t_ch[i]) you sum up in your documentation from j=0 to j=i (see attachment). In your example code 
read_binary.cpp (line 113) you sum from j=0 to j=i-1. Since you get the the bin with in the binary file, I guess that the example code is correct one?

Thank you very much,
Cheers,
Roman
  363   Wed Aug 13 20:17:19 2014 Roman Gredigbinary files time calibration header in drs-5.0.2
Dear Stefan

I have a problem considering binary data files.
Usually binary files start with TIME... (the time calibration header). But I observed the following reproducible problem.
1. Start to save a binary file (e.g. 001.dat) with 1000000 events. 
2. Hit the close button before this limit has reached. (so far the binary files seems to be ok) 
3. Start to save again a file with the SAME filename (and agree to replace the already existing it)
If I do it like this, the file has no time information anymore and starts directly with EHDR.

could it be that the m_evSerial counter is not reset in this specific situation?

Cheers,
Roman
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