I'm writing the drs_exam.cpp to use multi-boards(v3, firmware:4.0.0), and taking data succeeded. But I have several questions about function written in DRS.cpp.

1. I wrote following code in drs_exam.cpp to set input range -0.4~0.6

                                     b1->SetInputRange(0.1);

            And the 100mV offset appeared(I attached a picture). I think this is due to the voltage calibration isn't done.(Calibrated to -0.5~0.5mV in DRS Oscilloscope)

            If so, could you show me a simple usage of "CalibrationWaveform()" function in DRS.cpp? (or other function?)

       2. Although this question might be the almost same with above, is there any way to execute voltage and timing calibration in drs_exam.cpp?

           Now I start DAQ by executing drs_exam.cpp after I execute voltage and timing calibration to each board by DRS Oscilloscope program.

      3. Which command is right to use external trigger?

                                   b1->SetTriggerSource(4);   or  b1->SetTriggerSource(1<<4);

Best regards,

Toshihiro Nonaka

 Does it give the ability to measure triggering rate? I'm talking again about possibility of use DRS4 as pulse counter for PMT's. If yes, do I need new v5 board or it is possible to use v4 board?

Yes it is possible to measure the raw trigger rate, with a resolution of 10 Hz. You need a new V5 board for that. 

Dear Stefan

I have two questions concerning the best time resolution with the DRS V5 eval board.
a) Calibration:
I am using 4 boards daisy chained. To achieve optimal time resolution I did first a voltage calibration and right afterwards a time calibration. For all 
boards after the master I am not sure how to do it.
After setting the flag "Configure multi-board daisy-chain" in the config menu, all the slave boards set the flag "use external reference clock".  By 
hitting the voltage calibration button, the slave boards unset this flag. Is it true, that I have to re-set this before doing the time-calibration right 
afterwards?


b) getting the right times in binary format:
To get the time out of the time width (i.e. the t_ch[i]) you sum up in your documentation from j=0 to j=i (see attachment). In your example code 
read_binary.cpp (line 113) you sum from j=0 to j=i-1. Since you get the the bin with in the binary file, I guess that the example code is correct one?

Thank you very much,
Cheers,
Roman

> a) Calibration:
> I am using 4 boards daisy chained. To achieve optimal time resolution I did first a voltage calibration and right afterwards a time calibration. For all 
> boards after the master I am not sure how to do it.
> After setting the flag "Configure multi-board daisy-chain" in the config menu, all the slave boards set the flag "use external reference clock".  By 
> hitting the voltage calibration button, the slave boards unset this flag. Is it true, that I have to re-set this before doing the time-calibration right 
> afterwards?

Please do NOT do any calibration in multi-board mode. This will not work. Calibrate the boards separately, then activate the multi-board mode. Please note that the timing between the boards is not better 
than ~50 ps. This is a limitation of the FPGA clock generators. If you need better timing, you have to feed an external clock into one channel of each board (leaving only 3 channels for DAQ). The upcoming 
WaveDREAM board will have 16 channels per board, so building bigger DAQ systems will be much easier (and more precise).

> b) getting the right times in binary format:
> To get the time out of the time width (i.e. the t_ch[i]) you sum up in your documentation from j=0 to j=i (see attachment). In your example code 
> read_binary.cpp (line 113) you sum from j=0 to j=i-1. Since you get the the bin with in the binary file, I guess that the example code is correct one?

Yes, I will correct the documentation.

Cheers,
Stefan

1. b->CalibrateVolt(NULL);

2. see 1.

3. For the V3 boards use b->SetTriggerSource(4), for V4 and V5 boards, use b->SetTriggerSource(1<<4). I had to change that because from V4 on we can have logical combinations between channels (like channel 1 AND channel 2).

Best regards,

Stefan 

I'm not sure if I understand you correctly. The trigger rate could be up to 200 MHz, and it's possible to measure it  with 10 Hz resolution. Is it right?

Does it possible to measure independent trigger rate for each channel?

 hi Stefan,can you update the code to convert binary to root for newest drsosc?Thanks.

Hello,

Indeed you only need R99-R106 to be installed. Unfortunately the firm/software cannot know if the resistors are there, that's why we introduced R142/R143, which connect J44 of the FPGA optionally to low. So if J44 is low (R143 installed), this tells the system that we are in 2048 bin mode. Unfortunately you need firmware revision 21305 or later to support this bit, which you apparently do not have. So you can either upgrade the firmware (if you have a download cable) or "fake" the 2048 bin mode in software. Go to line 4345 of DRS.cpp and look for DRSBoard::Is2048ModeCapable(). This function just returns the status of this bit. If you installed R99-R106, you could modify this function to always return "1" instead of "0". Then the DRSOsc program will display 2048 bins for each of the four channels.

Best regards,

Stefan 

 Hello!

I have a question concerning the sampling speed of the DRS4 evaluation board.

It is written in the manual that the sampling speed of  DRS4 Evaluation Board is supported above 0.7 GHz.

However I was able to set the sampling speed to be 0.5 GHz with the function DRSBpard::SetFrequency(0.5)  and realized that DRSBoard::GetTime function fills time array in every 2 ns.

I am wondering if the data taken with 0.5 GHz sampling is reliable or not.

Best regards,

Tsutomu Nagayoshi

Stefan Ritt wrote:

Please find attached a simple ROOT based program (http://root.cern.ch) to decode binary data from the DRSOsc program. It assumes that all four channels were recorded. If this is not the case, the program can be adjusted accordingly. To use it, simply type (assuming that you have written a data file "test.dat" with DRSOsc): root [0] .L decode.C+ Info in <TUnixSystem::ACLiC>: creating shared library /tmp/./decode_C.so root [1] decode("test"); Info in <TCanvas::MakeDefCanvas>:  created default TCanvas with name c1 1927 events processed "test.root" written root [2]  If you have turned on the clock on channel4 of the DRS4 evaluation board, it will produce a plot like this:       /Stefan

I updated this ROOT program for the new format used with the V5 boards. It's now called "read_binary.C". Usage stays the same. There is also a standalone C program "read_binary.cpp". Both are attached. 

See elog:361 

Dear Stefan

I have a problem considering binary data files.
Usually binary files start with TIME... (the time calibration header). But I observed the following reproducible problem.
1. Start to save a binary file (e.g. 001.dat) with 1000000 events. 
2. Hit the close button before this limit has reached. (so far the binary files seems to be ok) 
3. Start to save again a file with the SAME filename (and agree to replace the already existing it)
If I do it like this, the file has no time information anymore and starts directly with EHDR.

could it be that the m_evSerial counter is not reset in this specific situation?

Cheers,
Roman

 Hi, I read its possible to use channels 2,4,6 to extend 200ns to 400ns (1024bins to 2048).

Is it possible to use same channels to double sampling rate with paralel feeding, one channel delayed by Ts/2, for 5,12GS/s is it cca 3cm delay cable?

Martin

In principle yes (you could split your signal externally and add some cable delay to one side), but it is not supported by the software. You would have to combine the data from the two channels yourself. But it won't help much. The analog bandwidth of the evaluation board is about 700 MHz. So sampling at 10 GSPS vs. 5 GSPS won't give you any additional information, since the highest frequencies in your signal will be only 700 MHz. You could as well take your 5 GSPS measurement and interpolate it with some sinc function to get exactly the same result. See here for details: http://en.wikipedia.org/wiki/Whittaker%E2%80%93Shannon_interpolation_formula 

Dear Stefan

after having some problems with writing binary files with more than 4 drs boards (in multiboard-mode) I might 
have found the solution.
In the file src/Osci.cpp at line 838 is: 
unsigned char buffer[100000];

If I understand the binary format right, this works only with up to four boards. With the maximum number of 
boards in your specification (16 boards) and all channels switched on on all boards this array needs to have 
about 400000 entries (for the first event, where the time information is written too).

Could you please cross-check that?

Thank you very much!
Cheers,
Roman

 Hi everyone,

Has anyone tried to synchronize 2 (two) DRS4 evaluation boards readout by the same computer? I have read about some attempts on this board in the past, but I do not know if they have succeeded. If yes, could you share your experience and/or software.

Thank you very much,

Dmitry.

Please read the manual http://www.psi.ch/drs/DocumentationEN/manual_rev50.pdf page 25 where this is described in detail.

/Stefan

 Hi Stefan,

Thank you for pointing me to the document. Does it apply only to version 5 of the board or can it be applied also to version 4 (which is the one I have)?

Dmitry