| ID |
Date |
Author |
Subject |
Text |
 |
|
554
|
Tue Nov 8 10:20:52 2016 |
Stefan Ritt | Missing Header | The web page from where you downloaded
the software contains a sentence "requires
libusb-1.0 package". Please install |
|
|
553
|
Fri Nov 4 17:41:03 2016 |
Christian Farina | Missing Header | Hello everybody,
I am completely new to this, so
please bear with me. |
|
|
552
|
Fri Oct 28 15:51:59 2016 |
Stefan Ritt | Problems with DRS command line | No, I absolutely have no idea. Both DRSOsc
and drscl use exaclty the same code to access
USB.
|
|
|
551
|
Fri Oct 28 15:02:18 2016 |
Simon Mendisch | Problems with DRS command line | [quote="Stefan Ritt"]
You are the first one describing this problem
(out of ~200 people), so I guess the problem |
|
|
550
|
Thu Oct 27 08:29:26 2016 |
Stefan Ritt | Problems with DRS command line | [quote="Alexey Lubinets"]Hello, everybody
I have installed the software for the DRS4 |
|
|
549
|
Wed Oct 26 21:15:35 2016 |
Alexey Lubinets | Problems with DRS command line | Hello, everybody
I have installed the software for the DRS4 |
|
|
548
|
Tue Oct 11 22:11:26 2016 |
Stefan Ritt | time difference between 2 channels only ~30-35ps @ 5GSmples/s | Thank you very much! I will check it tomorrow!
-d
Concerning the offset, it looks |
|
|
547
|
Tue Oct 11 09:20:04 2016 |
Stefan Ritt | time difference between 2 channels only ~30-35ps @ 5GSmples/s | Concerning the offset, it looks to me like
you moved the offset slider slider of channel
1 to a non-zero position. You see that from |
|
|
546
|
Tue Oct 11 09:04:33 2016 |
Danny Petschke | time difference between 2 channels only ~30-35ps @ 5GSmples/s | Hello Stefan,
thanks for the paper. That makes
sense. I thought about sth. like that but |
|
|
545
|
Mon Oct 10 12:03:27 2016 |
Stefan Ritt | time difference between 2 channels only ~30-35ps @ 5GSmples/s | Ok, I got it. The timing resolution is
affected by the signal-to-noise ratio over
the rise-time of your signal. You find the |
|
|
544
|
Mon Oct 10 11:30:37 2016 |
Danny Petschke | time difference between 2 channels only ~30-35ps @ 5GSmples/s | Hello Stefan,
Chn2 & Chn3 were used for delay-determination as
you can see on the second picture. |
|
|
543
|
Sun Oct 9 11:39:18 2016 |
Stefan Ritt | time difference between 2 channels only ~30-35ps @ 5GSmples/s | Can you post a screenshot of your measurement?
Stefan
|
|
|
542
|
Sun Oct 9 10:43:35 2016 |
Danny Petschke | time difference between 2 channels only ~30-35ps @ 5GSmples/s | (Board Type:9, DRS4)
Hello,
I´m trying to reach the timig |
|
|
541
|
Thu Oct 6 15:23:18 2016 |
Will Flanagan | | Hi Stefan,
That is exactly what I'm looking
for. Thanks again! |
|
|
540
|
Thu Oct 6 11:18:05 2016 |
Stefan Ritt | Timestamp for each DRS4 waveform | In the mentioned read_binary.cpp file you
have the line where you read the event header
i = fread(&eh, sizeof(eh), |
|
|
539
|
Wed Oct 5 22:43:29 2016 |
Will Flanagan | Timestamp for each DRS4 waveform | Hi DRS4 Experts,
I have been analyzing DRS4 binary
data with scripts based on Stefan's (very |
|
|
538
|
Fri Sep 30 17:03:38 2016 |
Stefan Ritt | Output Timing Drifting | Hi Jacob,
you are missing the timing calibration.
Each sampling cell has not the same width. |
|
|
537
|
Thu Sep 29 17:26:13 2016 |
Jacob Hwang | Output Timing Drifting | Hello,
I have designed four DRS4 chips
(36 channels) on my board running at 1GHz |
|
|
536
|
Mon Aug 29 12:51:48 2016 |
Stefan Ritt | increment write config register on the fly? | The problem is when you change the write
config register from 11111111 to 01111111,
or from 00001111 to 00000111, then the last |
|
|
535
|
Mon Aug 29 12:18:49 2016 |
benjamin legeyt | increment write config register on the fly? | If I may trouble you for a little more
information, the critical point then is
that there should not be any zeroes in the |
|