| ID |
Date |
Author |
Subject |
Text |
 |
|
823
|
Fri Apr 9 20:29:45 2021 |
Sean Quinn | Spikes/noise sensitive to clock settings? | Dear DRS4 team,
I'm trying to troubleshoot
some odd spike behavior. If I run the ADC |
|
|
825
|
Fri Apr 9 21:38:59 2021 |
Stefan Ritt | Spikes/noise sensitive to clock settings? | elog:824
|
|
|
885
|
Fri Jun 24 09:57:36 2022 |
LynseyShun | Spikes/noise sensitive to clock settings? | Hello, I now have periodic spikes in CH0
and CH1 output. How can I eliminate
these spikes? I'm sorry I didn't |
|
|
888
|
Fri Jul 29 17:23:43 2022 |
Stefan Ritt | Spikes/noise sensitive to clock settings? | Look at the DRS4 data sheet, Figure 12.
You see there the rising SRCLK pulse which
outputs the next analog value. You also see |
|
|
348
|
Tue May 27 13:46:18 2014 |
Dominik Neise | Spikes in DRS4 data on custom baord. | We see quite some spikes in our DRS4 sampled
data in FACT. We see different types
of spikes: |
|
|
349
|
Tue May 27 16:07:17 2014 |
Stefan Ritt | Spikes in DRS4 data on custom baord. |
|
|
|
289
|
Wed Aug 28 13:07:51 2013 |
Andrey Kuznetsov | Some bug fixes and questions | For http://www.psi.ch/drs/DocumentationEN/manual_rev20.pdf:
0 0x02 15..8 board_type 5 for DRS4
USB Evaluation Board 1.1 ---> should instead |
|
|
290
|
Thu Sep 5 10:01:00 2013 |
Andrey Kuznetsov | Some bug fixes and questions | #11 0x080589de in DRSBoard::GetWave (this=0xb7456008,
chipIndex=0, channel=0 '\000', waveform=0x40f24000,
responseCalib=true, triggerCell=207, wsr=0, |
|
|
291
|
Mon Sep 9 06:49:36 2013 |
Andrey Kuznetsov | Some bug fixes and questions | The DRSCallback *pcb is
missing an if statement in the code when
DRS Oscilloscope software isn't used when |
|
|
325
|
Wed Jan 15 16:15:00 2014 |
Stefan Ritt | Some bug fixes and questions |
|
|
|
326
|
Wed Jan 15 17:02:58 2014 |
Stefan Ritt | Some bug fixes and questions |
|
|
|
327
|
Wed Jan 15 17:11:14 2014 |
Stefan Ritt | Some bug fixes and questions |
|
|
|
332
|
Wed Mar 5 21:54:13 2014 |
Hermann-Josef Mathes | Software drs-5.0.0 fails to compile (drsosc) | Hi,
the latest software drs-5.0.0.tar.gz
fails to compile on my freshly installed |
|
|
333
|
Thu Mar 6 11:12:44 2014 |
Stefan Ritt | Software drs-5.0.0 fails to compile (drsosc) |
|
|
|
865
|
Wed Feb 16 14:06:45 2022 |
Dmitry Hits | Sliders missing in drsosc | Hi everyone,
Did anyone have a "missing
sliders problem" in GUI (see attachment) |
|
|
906
|
Thu Feb 22 01:21:11 2024 |
Rod McInnis | Simulation of FPGA | Hello:
A bit of background: I am
working on a project that is utilizing the |
|
|
907
|
Thu Feb 22 10:37:03 2024 |
Stefan Ritt | Simulation of FPGA | The Cypress has its own firmware, contained
in the distribution under firmware/CY7C68013A/drs_eval.c.
There you can see how the data is fetched. |
|
|
7
|
Tue Apr 28 11:44:07 2009 |
Stefan Ritt | Simple example application to read a DRS evaluation board | Several people asked for s simple application
to guide them in writing their own application
to read out a DRS board. Such an application |
|
|
8
|
Wed Apr 29 07:57:33 2009 |
Stefan Ritt | Simple example application to read a DRS evaluation board |
|
|
|
61
|
Mon Apr 5 17:57:41 2010 |
Heejong Kim | Simple example application to read a DRS evaluation board |
|
|