1. b->CalibrateVolt(NULL);

2. see 1.

3. For the V3 boards use b->SetTriggerSource(4), for V4 and V5 boards, use b->SetTriggerSource(1<<4). I had to change that because from V4 on we can have logical combinations between channels (like channel 1 AND channel 2).

Best regards,

Stefan 

> a) Calibration:
> I am using 4 boards daisy chained. To achieve optimal time resolution I did first a voltage calibration and right afterwards a time calibration. For all 
> boards after the master I am not sure how to do it.
> After setting the flag "Configure multi-board daisy-chain" in the config menu, all the slave boards set the flag "use external reference clock".  By 
> hitting the voltage calibration button, the slave boards unset this flag. Is it true, that I have to re-set this before doing the time-calibration right 
> afterwards?

Please do NOT do any calibration in multi-board mode. This will not work. Calibrate the boards separately, then activate the multi-board mode. Please note that the timing between the boards is not better 
than ~50 ps. This is a limitation of the FPGA clock generators. If you need better timing, you have to feed an external clock into one channel of each board (leaving only 3 channels for DAQ). The upcoming 
WaveDREAM board will have 16 channels per board, so building bigger DAQ systems will be much easier (and more precise).

> b) getting the right times in binary format:
> To get the time out of the time width (i.e. the t_ch[i]) you sum up in your documentation from j=0 to j=i (see attachment). In your example code 
> read_binary.cpp (line 113) you sum from j=0 to j=i-1. Since you get the the bin with in the binary file, I guess that the example code is correct one?

Yes, I will correct the documentation.

Cheers,
Stefan

Dear Stefan

I have two questions concerning the best time resolution with the DRS V5 eval board.
a) Calibration:
I am using 4 boards daisy chained. To achieve optimal time resolution I did first a voltage calibration and right afterwards a time calibration. For all 
boards after the master I am not sure how to do it.
After setting the flag "Configure multi-board daisy-chain" in the config menu, all the slave boards set the flag "use external reference clock".  By 
hitting the voltage calibration button, the slave boards unset this flag. Is it true, that I have to re-set this before doing the time-calibration right 
afterwards?


b) getting the right times in binary format:
To get the time out of the time width (i.e. the t_ch[i]) you sum up in your documentation from j=0 to j=i (see attachment). In your example code 
read_binary.cpp (line 113) you sum from j=0 to j=i-1. Since you get the the bin with in the binary file, I guess that the example code is correct one?

Thank you very much,
Cheers,
Roman

Yes it is possible to measure the raw trigger rate, with a resolution of 10 Hz. You need a new V5 board for that. 

 Does it give the ability to measure triggering rate? I'm talking again about possibility of use DRS4 as pulse counter for PMT's. If yes, do I need new v5 board or it is possible to use v4 board?

I'm writing the drs_exam.cpp to use multi-boards(v3, firmware:4.0.0), and taking data succeeded. But I have several questions about function written in DRS.cpp.

1. I wrote following code in drs_exam.cpp to set input range -0.4~0.6

                                     b1->SetInputRange(0.1);

            And the 100mV offset appeared(I attached a picture). I think this is due to the voltage calibration isn't done.(Calibrated to -0.5~0.5mV in DRS Oscilloscope)

            If so, could you show me a simple usage of "CalibrationWaveform()" function in DRS.cpp? (or other function?)

       2. Although this question might be the almost same with above, is there any way to execute voltage and timing calibration in drs_exam.cpp?

           Now I start DAQ by executing drs_exam.cpp after I execute voltage and timing calibration to each board by DRS Oscilloscope program.

      3. Which command is right to use external trigger?

                                   b1->SetTriggerSource(4);   or  b1->SetTriggerSource(1<<4);

Best regards,

Toshihiro Nonaka

All I know is that the  "20mV" spikes are always symmetrical around cell #512, that they are typically 17.4 mV in height, and that they occur always in all 9 channels simultaneously. They cannot occur in all locations, but there only like 32 possible locations where they can occur. With this information it should be easy to fix them by filtering.

200 mV spikes are new to me. I do not see them in our boards, so it must be related to the board readout and not to the chip.

Best regards,
Stefan
 

We see quite some spikes in our DRS4 sampled data in FACT.  We see different types of spikes:

• single cell spikes, usually showing a large amplitude of 200mV
• double cell spikes, usually only in the order of 20mV.
• Even triple and quadro cell spikes are rarely seen.

The double cell spikes often occur as symmetrical double cell spikes mirrored at cell 512. quadro cell spikes seem to be nothing else, than connected symmetrical double cell spikes. For the triple cell spikes we have no idea.
Currently we use simple filters to get rid of these spikes, this workes rather well for the large single cell spikes, but with the occurance of tripples and quadros we started to worry about higher multiples and revived our DRS4 spike investigations.

Now I was told, that you Stefan know already where these spikes come from and even a paper exisits. Unfortunately so far I was unable to find it.
I wonder if it is possible to predict the occurance of these spikes, so one does not have to search for them anymore and can get rid of the filters.

Best regards

Dominik

Unfortunately the simultaneous writing/reading does not work as described in the data sheet. Just recently we found out that due to a bug in the chip a part of the waveform is missing if you read and write at the same time. The only clean solution is to use two DRS4 chips in parallel. You read one chip while the other samples, then you switch over between them. In that case all the ROI scheme and channel cascading works normally. The dead time will be addressed by the DRS5 chip, which will be dead time free, but will not be available until in maybe 2-3 years.

/Stefan 

Hello!

We're developing electronics based on the DRS4 to read out a breast PET scanner and our event rate will be quite high so we're concerned about dead-time.  with that in mind, I have a question regarding the mode of simultaneous writing and reading that is described in the DRS4 data sheet.  I think the description there is quite clear but I'd like to ask for a few clarifications.

1) Are the channels required to be read out via the channel multiplexer when doing the simultaneous write/read or is it ok to read out all channels in parallel (even the ones still sampling) and just throw away the ones you don't want?

2) If one wanted to use region of interest mode along with the simultaneous write/read, how would that work?  Here is what I would think - please tell me if I'm missing some important detail:

-upon trigger, deassert dwrite.

-strobe RSRLOAD

-increment write config register

-reassert dwrite

-start the readout (reading out stop shift register value on SROUT as data comes out)

3) now to add even more complexity - I would actually like to use simultaneous write/read along with region of interest mode and also with pairs of cascaded channels as we need >500ns latency and 2Gsps is too slow for our signals.  the combination of cascading and simultaneous write/read is addressed in the data sheet but I still have one question.  In normal circumstances when cascading channels, one would read out the value in the write shift register to know which channel was active when the domino wave stopped.  I assume that this is not possible when dwrite is enabled as the write shift register is then advanced by the domino wave, so I see three possibilities:

-accept more dead-time and read out the write-shift-register each time (adds ~240ns to deadtime)

-just read out both channels every time and figure out later where is the data you want

-attempt to keep track of the expected state of write-shift-register in firmware.

is there a better option that I have not thought of?

many thanks!

Benjamin LeGeyt

Yes, but this is documented in the evaluation board manual. You have to modify the script slightly. I will update it myself in about 2-3 weeks.

Cheers,

Stefan

Thank you for your fast and very helpful replay.

I made it work with drsosc version 4 but with version 5 i am getting weird results. Is it possible that they changed binary formatting?

You look here: elog:262

/Stefan

Hi,

Does anybody have program for conversion from binary or xml to cern ROOT *.root file?
 

Thank you for any help you can provide,
Luka Pavelic


 

 Hi Stefan,

you were right, I forgot to install the libusb driver.

Thanks for your support

 Hi,

   I want to describe this phenomenon again. The diagram below is DRS4 output. There is no input signal. Green is the output8+, blue is the output8-. Output8+ of the first channel is below  the baseline. The output is saturation when input ADC. It is not right, and what is it  in front of the first channel? It seemed there are two channels.  Others channel  is suitable. I check the circuit , Hardware is no problem, so I want to konw where the FPGA code  is wrong. What reason is caused? Can anyone help me to solve the problem? Thanks!

> 
> Dear Stefan
> 
> I am trying to use the DRS4 eval board on a Windows7 machine. Unfortunately I get an error message saying "No DRS 
> board found". But I can see the DRS board in the device manager with the proper driver loaded. Is there any known 
> problem with win7?
> 
> I am using windows7 professional (SP1) with the drs software 5.0.1.
> 
> Cheers,
> Roman
> 
> PS: Everything is working on my mac. But not under windows7.

Hi Roman,

please read section 2.3. (page 13)  from the Evaluation Board manual: http://www.psi.ch/drs/DocumentationEN/manual_rev50.pdf

You have to update the USB driver in your Computer Management.

Cheers,
Stefan 

You are funny. Just by looking at a scope picture I should know what is wrong at your FPGA code. Unfortunately I'm not a magician. I looks to me like you have 11 channels in your diagram, although the chip has only 9. What I would recommend is to put some input to each channel one at a time, like a 10 MHz sine wave. You should then see that sine wave for the single channel at the output and can correlate input vs. output. Maybe your address bits are wrong or the chip has a soldering problem.

/Stefan 

Have a look at the web site http://www.psi.ch/drs/software-download . Under the MS Windows section it says that you have to install the libusb-1.0 package first before you can compile the example program. This is also obvious from the missing _usb_* functions in the error listing above.

/Stefan

 Hi,

 The diagram below is DRS4 output. Green is the output8+, blue is the output8-. Output8+ of the first channel is below  the baseline. It is not  right.

Others channel  is suitable. I check the circuit , Hardware is no problem, so I want to konw where the FPGA code  is wrong. what reason is caused? Thanks!