ELOG DRS4 Forum

triger for measuring time between pulses in channels

Stefan Ritt wrote:

Martin Petriska wrote:

Stefan Ritt wrote:

Martin Petriska wrote:

I have two BaF2 detectors with PMT connected to Ch1 and Ch2. At this time Im using external triger module to start DRS4. My evalution board is version 3 so I have no possibility to trigger on two or more pulses occurence on different channels. But I have this idea, trigger with analog trigger on channel 1 (start detector) will start measurement on all channels. After that using FPGA inside EVM to look if some value in Ch2 is bigger as treshold value for example 0,5V and if yes then send data by USB to PC, if signal in Ch2 is lower then restart measurement and wait on triger in Ch1. This way I want to eliminate false data transfer throw USB. Is this possible to implement it into DRS4 evaluation board firmware ?

Thanks.

It is muuuuch easier to upgrade to a V4 board!

Modification of firmware is not so easy. You have to learn and understand VHDL. Then, you have to add additional registers for this thresholds, which requires modification of the C library as well. The data inside the evaluation boards is not yet calibrated (this is only done on the C library), so you have an uncertainty of 30-40mV in this data.

Ok, except this, I would have a question regarding to the new trigering posibility in V4 board. At this time, I am using Ztec ZT4612 which has some pattern triger posibility. Output from this card is used as an external trigger. Regarding this I have found a problem. Pulses from PMT have about 5-8 ns width. But I need to measure time diferences between pulses in range from 0-50ns. Problem is, that coincidence between pulses is working only on short pulse area (5-8ns) when they are overlapped. Additionaly the result histogram of time diferences is proportional to the pulse shapes. I solve this problem enabling 20MHz LPF filter in ZT4612, so the pulses are wider and overlaped on larger area. But, how it is with the V4 board? Will it trigger if I have for example one 5ns pulse on begiinning of CH1 and second pulse for example 50 ns later on Ch2 with the same probability when pulses are in the same time position?

No.

Hello. I need to digitize pulses from two PMT. After pulse on first PMT I have to save all pulses from second PMT in range 200 ns (and starting pulse from the first, and time range between pulse from 1st PMT and pulses from 2nd PMT). Is it possible with DRS evaluation board?

166

Wed Jun 20 14:36:01 2012

triger for measuring time between pulses in channels

Stefan Ritt wrote:

Ivan Petrov wrote:

If you run at 2 GSPS, you have a time window of 500 ns like on an oscilloscope. If you trigger on 1st PMT, you will get the traces of all 4 inputs for the next 500 ns. So I guess this is what you want.

Ok. And, If I understand correctly, the main bottleneck in data readout is USB. I.e., theoretically maximum readout rate is 500 Hz. Is it true?

170

Mon Jul 9 14:14:48 2012

Problem compiling drs_exam.cpp on windows

Hello again. I have not got evaluation board yet, but already faced some difficulties:) I'm trying to compile drs_exam.cpp on Windows 7 using dev-c++ with imagelib-2 and WxWindows 2.4.2 DevPaks installed, but nothing works. Compile log is attached. Honestly, I'm not very familiar with c++, so any suggestions will be helpful. Thank you.

Attachment 1: compile_log.txt

Compiler: Default compiler
Building Makefile: "G:\devcpp\Makefile.win"
Executing  make...
make.exe -f "G:\devcpp\Makefile.win" all
g++.exe -c AboutDialog.cpp -o AboutDialog.o -I"C:/Dev-Cpp/lib/gcc/mingw32/3.4.2/include"  -I"C:/Dev-Cpp/include/c++/3.4.2/backward"  -I"C:/Dev-Cpp/include/c++/3.4.2/mingw32"  -I"C:/Dev-Cpp/include/c++/3.4.2"  -I"C:/Dev-Cpp/include"   

In file included from C:/Dev-Cpp/include/wx/wx.h:15,
                 from DRSOscInc.h:7,
                 from AboutDialog.cpp:7:
C:/Dev-Cpp/include/wx/defs.h:179: error: redeclaration of C++ built-in type `int'

In file included from C:/Dev-Cpp/include/wx/memory.h:20,
                 from C:/Dev-Cpp/include/wx/object.h:25,
                 from C:/Dev-Cpp/include/wx/wx.h:16,
                 from DRSOscInc.h:7,

                 from AboutDialog.cpp:7:
C:/Dev-Cpp/include/wx/string.h:160:4: #error "Please define string case-insensitive compare for your OS/compiler"
In file included from DRSOscInc.h:12,
                 from AboutDialog.cpp:7:
DRSOsc.h:38:26: wx/hyperlink.h: No such file or directory
In file included from DRSOscInc.h:12,

                 from AboutDialog.cpp:7:
DRSOsc.h:532: error: ISO C++ forbids declaration of `wxHyperlinkCtrl' with no type
DRSOsc.h:532: error: expected `;' before '*' token

make.exe: *** [AboutDialog.o] Error 1

Execution terminated

172

Wed Jul 11 10:04:51 2012

Problem compiling drs_exam.cpp on windows

Stefan Ritt wrote:

Ivan Petrov wrote:

I have no experience with dev-c++, so I cannot be of help here. The supported systems are Linux and Windows with MS Visual C++. But it looks like the problems are related to compiling wxWidgets, which actually you do NOT need for drs_exam.cpp. The wxWidgets library is only needed for the DRSOsc application. If you want to compile it anyhow, first learn how to compile standard WxWidgets applications from

http://www.wxwidgets.org/docs/tutorials/devcpp.htm

Best regards,

Stefan

Ok, this was my bad, I added some unnecessary files to project. Drs_exam compiles well with ms vc++. Thanks!

764

Thu Jul 18 01:03:44 2019

Ismael Garcia

Trace Impedance

Hi Steffan,

I'm an engineer at UCLA developing a board with the DRS4 chip. Our team has a question on what might be the required trace impedence for the analog inputs. Can that information be provided?

Best Regards,
Ismael Garcia

Attachment 1: DRS4_Analog_IN.PNG

766

Fri Jul 19 01:37:09 2019

Ismael Garcia

Trace Impedance

When you're refering to laying a 50 Ohm trace, you're referring to the SMA input and not the interface between the output of the Op-AMP(THS4508) buffer
and the inputs of the DRS4(IN0-IN8). Is there a recommended diffential impedance for IN0-IN8?

Ismael

Stefan Ritt wrote:

The requiremnet is the same as for any high speed analog board, there is othing special with the DRS4. If you want to terminate your line with 50 Ohms and you want a matched impedance layout, you route all lines with 50 Ohms impedance. Truth is however that nothing is perfect. The SMA connector is not exactly 50 Ohm, the PCB gets a 10-20% variation depending on the manufacturer. So even if you try hard, you will never have a 50 Ohm matched impedance. On the evaluation board we made some compromises as you have seen, but for us the board works satisfactory even with this compromises, and you can test it yourself with real hardware (namely the evaluation board). If you can do a better job, try it. But usually these compromises have only little influence on the signal quality.

Stefan

Ismael Garcia wrote:

Hi Steffan,

I'm an engineer at UCLA developing a board with the DRS4 chip. Our team has a question on what might be the required trace impedence for the analog inputs. Can that information be provided?

Best Regards,
Ismael Garcia

421

Tue May 19 14:14:45 2015

Ilja Bekman

DRS4 firmware UCF constraints

Hello, I'm using two DRS4 rev.5 boards for 8ch readout and triggering.

I needed to modify the trigger logic and implement some tweaks in the firmware, and noticed that 
the firmware source in drs-5.0.2 (and 5.0.3, SVN:5339) while still compiling fine with Xilinx ISE 10, stops
doing so in the ISE 14.7 (also already in 13.2)

While the Synthesis is running through (in the new ISE it complains about using more than 100% of resources.)
The Mapping fails due to constraints (firmware/ucf/drs4_eval5.ucf) complaining about an illegal IOSTANDARD
for P_IO_PMC_USR<55> (LVDS_25).

In the newer version the wild-cards (lines 67..69 ) are not properly dealt with, it seems, and if I move the
property by hand to all the wild-carded NETs it start to recognise the LVDS_25.
But after that Place&Route fails with messages about locked Banks due to incompatible VCCO.

I'm trying to adapt the ucf file and am reading about the changes in the ISE software and constraints files, but
want to ask if some of you guys have seen the same issue and resolved it out "officially".

Draft

Wed Oct 7 13:06:34 2015

Ilja Bekman

Voltage Calibration with signal on the input

Sun May 2 18:36:14 2010

Hi all,

i'm an electronics engineering student at UCM (Madrid) working on my master's thesis within the CTA collaboration. I'm designing the readout electronics for the telescope's camera, and i'm focusing in using GAPDs instead of PMTs and using the domino chip for the sampling of the signal. I was wondering if there is a spice and/or RF model of the DRS4 chip available. It would be very useful to perform some simulations before deciding to use the chip as the sampling solution for our prototypes.

If the answer is negative, can you give me some advise for modelling the chip in spice? Have you done any simulations?

Thanks in advance,

Ignacio Diéguez Estremera.

Mon May 3 17:06:02 2010

Stefan Ritt wrote:

Ignacio Diéguez Estremera wrote:

Hi all,

If the answer is negative, can you give me some advise for modelling the chip in spice? Have you done any simulations?

Thanks in advance,

Ignacio Diéguez Estremera.

Yes there is a transistor-level spice model, which I used to design the chip, but you won't be happy with it: Given the 500,000+ transistors on the chip, a 100 ns simulation takes a couple of weeks. We tried to make a simplified model just for the analog input using some measured S-parameters, but found that the RF behavior of the chip is almost impossible to describe to better than let's say 50%. In the end you have to fine-tune your analog front-end experimentally, to obtain optimal bandwidth. We are just working on a reference design with gives you 850 MHz bandwidth using an active input buffer.

Thanks for the information.

I would like to try the huge :-) model. Can you send it to my email address? Since the input signal are pulses of a few nanoseconds at FHWM, the simulation time may be reduced. I will post some feedback in the forum once i give it a try.

Kind regards.

Mon May 3 23:21:55 2010

Stefan Ritt wrote:

Ignacio Diéguez Estremera wrote:

Stefan Ritt wrote:

Ignacio Diéguez Estremera wrote:

Hi all,

If the answer is negative, can you give me some advise for modelling the chip in spice? Have you done any simulations?

Thanks in advance,

Ignacio Diéguez Estremera.

Thanks for the information.

Kind regards.

I just checked and realized that we are not allowed to give out the "huge" model since it contains parameters from the chip manufacturer's library which are confidentially.

Thank you for the effort anyway.

So i guess i won't be able to include drs4 in my simulations :-(. Any other suggestions? Maybe the S-params model you where working on? Anything is better than nothing :-)

Tue May 4 16:23:16 2010

Stefan Ritt wrote:

Ignacio Diéguez Estremera wrote:

So i guess i won't be able to include drs4 in my simulations :-(. Any other suggestions? Maybe the S-params model you where working on? Anything is better than nothing :-)

Please find attached the S-parameters.

Thanks :-)

Wed May 5 22:30:50 2010

Random noise spec in datasheet

Hi,

According to DRS4's datasheet, the random noise is 0.35mVrms. Is this the input equivalent noise voltage? It is computed over the 0-950MHz frequency band?

Regards.

636

Fri Nov 3 12:11:14 2017

H�kan Wennl�f

Triggering using AND

Hi!

I'm using the DRSOsc program, and I have a question that I need a bit clarified;

When triggering using AND between two channels, am I then triggering on rising/falling edge of both channels, or on the actual values?

That is, is it the change in value that it triggers on, or when the actual value goes above a certain threshold?

Using AND, it seems like I get a trigger when one (CH2) is above its trigger value (sometimes quite far above), and the other (CH1) changes to go above its trigger value. This works for my purposes, which is nice, but I just want to be sure I understand why it works. Ideally, I'd like to trigger when one of my channels is above a certain value, and the other has a rising edge above a certain value.

I'm sorry if it's a silly question! I've just noticed that the Keysight oscilloscopes I've used can only do one channel with a rising edge at a time when doing a logic trigger, and I thought the same thing might be going on in the background here (which would be ideal for my purposes).

Kind regards,

Håkan Wennlöf

681

Tue May 1 02:00:40 2018

Hyunseong Kim

DRS4 using drs_exam.cpp to save as binary files

Hi,

I would like to save the waveform in a .dat binary file using drs_exam.cpp.

I know the distributed software allows us to save as binary files with the save button, but I currently need to save multiple runs using a script.

I've seen that drs_exam.cpp can save the waveform as .txt files.

Is there any .cpp file or function that allows us to save the waveforms in binary format (.dat)?

Thank you for your help.

269

Fri Jul 5 12:46:45 2013

Missing methods in drs-4.0.1.tar.gz

Hi,

while trying to create python bindings for the DRS stuff using SWIG 2.0.4, two undefined methods prevent the python interpreter from loading the generated shared library. These methods are:

int DRSBoard::SetADCActive(unsigned char)
bool ResponseCalibration::Calibrate(unsigned int,unsigned int,float *,float *,float,bool)

Can we safely removed those methods from the DRS header files or (what I have actually done) is it better to fake some empty implementation in the input file to SWIG?

Another minor issue is that the python interpreter always terminates with a SegFault after script termination. I had not yet time to track that down...

Thanks & regards

Hermann-Josef

282

Wed Aug 7 15:05:59 2013

Repeated time calibration

Hi,

is there any (obvious) reason why it is not possible (or not indended) to repeat the time calibration of a DRS4 eval board several times. I get the shown error message from the 'drscl' tool as well when I try to call the corresponding method in the support library:

mathes@ikauger5:~/src/DRS4> drs-4.0.1/drscl
DRS command line tool, Revision 20430
Type 'help' for a list of available commands.

Found DRS4 board 0 on USB, serial #2362, firmware revision 17662

B0> tcalib
Enter calibration frequency [GHz]: 5
Creating Timing Calibration of Board #2362
[==================================================]
B0> tcalib 5
Creating Timing Calibration of Board #2362
Error performing timing calibration, please check waveforms

As I will be in holidays, the answer is not urgent.

Thanks

-- Hermann-Josef

284

Wed Aug 7 15:20:33 2013

Repeated time calibration

Stefan Ritt wrote:

Hermann-Josef Mathes wrote:

Hi,

As I will be in holidays, the answer is not urgent.

Thanks

-- Hermann-Josef

Ups, this is certainly a bug. Try to restart drscl between calibrations. Anyhow the calibration is poor (~20ps), so in a month or two we will have a much better one (~3ps), but that needs a new board (then will be called V5).

/Stefan

Hi Stefan,

thanks for the quick reply, I know that this solution works with drscl but not within my code.

I tried to track it down, but gave up very soon. Seems as if AnalyzeWF() which is called by CalibrateTiming() finds to much zero-crossings when it is called the second time.

Regards

-- Hermann-Josef

332

Wed Mar 5 21:54:13 2014