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Fri Feb 26 18:33:52 2021, Tom Schneider, Trouble getting PLL to lock        Fri Feb 26 21:24:39 2021, Tom Schneider, Trouble getting PLL to lock        Fri Feb 26 22:52:13 2021, Tom Schneider, Trouble getting PLL to lock        Thu Mar 4 21:36:14 2021, Tom Schneider, Trouble getting PLL to lock    Thu May 29 04:22:43 2014, Toshihiro Nonaka, CalibrationWaveform    Wed Apr 27 08:14:14 2016, Toshihiro Nonaka, serial number problem         Wed Apr 27 09:51:37 2016, Toshihiro Nonaka, serial number problem     Wed Jul 12 04:24:39 2017, Toshihiro Nonaka, Time resolution between boards    Wed Jan 17 09:51:16 2018, Tran Cong Thien, The input signals recorded are different with the signal showed in oscilloscope     Wed Jul 30 11:38:58 2014, Tsutomu Nagayoshi, Sampling speed of DRS4 Board ver4    Tue Jan 31 01:37:35 2017, VO HONG HAI, LLD and ULD discriminations,    Tue Oct 17 14:58:58 2017, Vadym Denysenko, Time offset         Wed Oct 18 11:48:14 2017, Vadym Denysenko, Time offset         Thu Jul 20 13:00:44 2017, Volodymyr Rodin, Driver installation on Windows 10    Fri Jul 21 09:16:02 2017, Volodymyr Rodin, Time output        Tue Jul 25 14:47:05 2017, Volodymyr Rodin, Time output    Wed Apr 16 03:22:43 2014, Wang , why is the first channel output error?     Thu Apr 17 12:02:28 2014, Wang , The first channel is wrong.    Tue Nov 3 22:37:56 2015, Will Flanagan, Latest macro for DRS4 V5        Tue Nov 3 23:15:38 2015, Will Flanagan, Latest macro for DRS4 V5

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