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    Reply  Fri Feb 26 18:33:52 2021, Tom Schneider, Trouble getting PLL to lock 
    Reply  Fri Feb 26 21:24:39 2021, Tom Schneider, Trouble getting PLL to lock 
    Reply  Fri Feb 26 22:52:13 2021, Tom Schneider, Trouble getting PLL to lock 
    Reply  Thu Mar 4 21:36:14 2021, Tom Schneider, Trouble getting PLL to lock 
Entry  Thu May 29 04:22:43 2014, Toshihiro Nonaka, CalibrationWaveform offset.png
Entry  Wed Apr 27 08:14:14 2016, Toshihiro Nonaka, serial number problem  serial.png
    Reply  Wed Apr 27 09:51:37 2016, Toshihiro Nonaka, serial number problem  
Entry  Wed Jul 12 04:24:39 2017, Toshihiro Nonaka, Time resolution between boards 
Entry  Wed Jan 17 09:51:16 2018, Tran Cong Thien, The input signals recorded are different with the signal showed in oscilloscope  
Entry  Wed Jul 30 11:38:58 2014, Tsutomu Nagayoshi, Sampling speed of DRS4 Board ver4 
Entry  Tue Jan 31 01:37:35 2017, VO HONG HAI, LLD and ULD discriminations, 
Entry  Tue Oct 17 14:58:58 2017, Vadym Denysenko, Time offset  
    Reply  Wed Oct 18 11:48:14 2017, Vadym Denysenko, Time offset  
    Reply  Thu Jul 20 13:00:44 2017, Volodymyr Rodin, Driver installation on Windows 10 
Entry  Fri Jul 21 09:16:02 2017, Volodymyr Rodin, Time output 
    Reply  Tue Jul 25 14:47:05 2017, Volodymyr Rodin, Time output 
Entry  Wed Apr 16 03:22:43 2014, Wang , why is the first channel output error?  QQ??20140416090124.jpg
Entry  Thu Apr 17 12:02:28 2014, Wang , The first channel is wrong. QQ??20140417174309.jpg
Entry  Tue Nov 3 22:37:56 2015, Will Flanagan, Latest macro for DRS4 V5 
    Reply  Tue Nov 3 23:15:38 2015, Will Flanagan, Latest macro for DRS4 V5 
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